[llvm-commits] [PATCH] Fix big-endian codegen bug in DAGTypeLegalizer::ExpandRes_BITCAST

[Ulrich Weigand]

Hi Duncan,

> > Hi Duncan, thanks for the review.  Unfortunately Altivec doesn't
support
> > 32-byte vector types ...
>
> I forgot that one end of the bitcast has to have a legal type...
>
> > I tried doing something with attribute ((vector_size (32))), but those
> > types are not passed in registers, and when accessing variables that
> > already reside in memory, the broken code path in ExpandRes_BITCAST
> > isn't being used in the first place, so I wasn't able to show the
problem.
> >
> > Any suggestions how to construct a test case that exposes the problem
> > for 32-byte vectors would be appreciated!
>
> If you are sure that the code does the right thing no matter how many
times
> the loop is executed, then I think it is OK to commit with the existing
> testcase.

Yes, this needs to be done on every pass through the loop.  For example,
with a 32-byte vector we'd have an <8 x i32> intermediate.  The first
pass through the loop would pair up vector elements:
  0, 1 -> new list element 8
  2, 3 -> new list element 9
  4, 5 -> new list element 10
  6, 7 -> new list element 11
In each of those operations, the lower-numbered element is the *high*
part of the pair on big-endian systems.

Now, on the next pass through the loop, we're getting again pairs:
  8, 9   and   10, 11
And again, the lower-numbered element must be the high part of the pair.

Finally, the pair 8,9 is the Hi part of the result and the pair 10,11
the Lo part of the results.

All in all, the original vector element 0 needs to end up in the most
significant bytes of the i256 result, so in every iteration step,
the element that contains the original vector element 0 must be
considered the high part of the pair being combined.

I've now checked this in.  Thanks again!


Mit freundlichen Gruessen / Best Regards

Ulrich Weigand

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