[llvm-commits] [llvm] r165783 - in /llvm/trunk: lib/Target/Mips/Mips16InstrInfo.cpp lib/Target/Mips/Mips16InstrInfo.td test/CodeGen/Mips/div.ll test/CodeGen/Mips/div_rem.ll test/CodeGen/Mips/divu.ll test/CodeGen/Mips/divu_remu.ll test/CodeGen/Mips/rem.ll test/CodeGen/Mips/remu.ll
Reed Kotler
rkotler at mips.com
Thu Oct 11 19:01:10 PDT 2012
Author: rkotler
Date: Thu Oct 11 21:01:09 2012
New Revision: 165783
URL: http://llvm.org/viewvc/llvm-project?rev=165783&view=rev
Log:
Div, Rem int/unsigned int
Added:
llvm/trunk/test/CodeGen/Mips/div.ll
llvm/trunk/test/CodeGen/Mips/div_rem.ll
llvm/trunk/test/CodeGen/Mips/divu.ll
llvm/trunk/test/CodeGen/Mips/divu_remu.ll
llvm/trunk/test/CodeGen/Mips/rem.ll
llvm/trunk/test/CodeGen/Mips/remu.ll
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp?rev=165783&r1=165782&r2=165783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.cpp Thu Oct 11 21:01:09 2012
@@ -58,12 +58,22 @@
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
- unsigned Opc = 0, ZeroReg = 0;
+ unsigned Opc = 0;
+
+ if (Mips::CPU16RegsRegClass.contains(DestReg) &&
+ Mips::CPURegsRegClass.contains(SrcReg))
+ Opc = Mips::MoveR3216;
+ else if (Mips::CPURegsRegClass.contains(DestReg) &&
+ Mips::CPU16RegsRegClass.contains(SrcReg))
+ Opc = Mips::Move32R16;
+ else if ((SrcReg == Mips::HI) &&
+ (Mips::CPU16RegsRegClass.contains(DestReg)))
+ Opc = Mips::Mfhi16, SrcReg = 0;
+
+ else if ((SrcReg == Mips::LO) &&
+ (Mips::CPU16RegsRegClass.contains(DestReg)))
+ Opc = Mips::Mflo16, SrcReg = 0;
- if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
- if (Mips::CPURegsRegClass.contains(SrcReg))
- Opc = Mips::Move32R16;
- }
assert(Opc && "Cannot copy registers");
@@ -72,9 +82,6 @@
if (DestReg)
MIB.addReg(DestReg, RegState::Define);
- if (ZeroReg)
- MIB.addReg(ZeroReg);
-
if (SrcReg)
MIB.addReg(SrcReg, getKillRegState(KillSrc));
}
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=165783&r1=165782&r2=165783&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Thu Oct 11 21:01:09 2012
@@ -118,6 +118,14 @@
FRR16<f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry),
!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
}
+
+//
+// maybe refactor but need a $zero as a dummy first parameter
+//
+class FRR16_div_ins<bits<5> f, string asmstr, InstrItinClass itin> :
+ FRR16<f, (outs ), (ins CPU16Regs:$rx, CPU16Regs:$ry),
+ !strconcat(asmstr, "\t$$zero, $rx, $ry"), [], itin> ;
+
class FRR16_M_ins<bits<5> f, string asmstr,
InstrItinClass itin> :
FRR16<f, (outs CPU16Regs:$rx), (ins),
@@ -196,6 +204,24 @@
// To do a bitwise logical AND.
def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
+//
+// Format: DIV rx, ry MIPS16e
+// Purpose: Divide Word
+// To divide 32-bit signed integers.
+//
+def DivRxRy16: FRR16_div_ins<0b11010, "div", IIAlu> {
+ let Defs = [HI, LO];
+}
+
+//
+// Format: DIVU rx, ry MIPS16e
+// Purpose: Divide Unsigned Word
+// To divide 32-bit unsigned integers.
+//
+def DivuRxRy16: FRR16_div_ins<0b11011, "divu", IIAlu> {
+ let Defs = [HI, LO];
+}
+
//
// Format: JR ra MIPS16e
@@ -551,5 +577,20 @@
// Small immediates
def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
+//
+// MipsDivRem
+//
+def: Mips16Pat
+ <(MipsDivRem CPU16Regs:$rx, CPU16Regs:$ry),
+ (DivRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
+
+//
+// MipsDivRemU
+//
+def: Mips16Pat
+ <(MipsDivRemU CPU16Regs:$rx, CPU16Regs:$ry),
+ (DivuRxRy16 CPU16Regs:$rx, CPU16Regs:$ry)>;
+
+
def: Mips16Pat<(add CPU16Regs:$hi, (MipsLo tglobaladdr:$lo)),
(AddiuRxRxImmX16 CPU16Regs:$hi, tglobaladdr:$lo)>;
Added: llvm/trunk/test/CodeGen/Mips/div.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/div.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/div.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/div.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 100, align 4
+ at jjjj = global i32 -4, align 4
+ at kkkk = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %div = sdiv i32 %0, %1
+; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+ store i32 %div, i32* @kkkk, align 4
+ ret void
+}
+
+
Added: llvm/trunk/test/CodeGen/Mips/div_rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/div_rem.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/div_rem.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/div_rem.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 103, align 4
+ at jjjj = global i32 -4, align 4
+ at kkkk = common global i32 0, align 4
+ at llll = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %div = sdiv i32 %0, %1
+ store i32 %div, i32* @kkkk, align 4
+ %rem = srem i32 %0, %1
+; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+ store i32 %rem, i32* @llll, align 4
+ ret void
+}
+
Added: llvm/trunk/test/CodeGen/Mips/divu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/divu.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/divu.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/divu.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 100, align 4
+ at jjjj = global i32 4, align 4
+ at kkkk = common global i32 0, align 4
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %div = udiv i32 %0, %1
+; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+ store i32 %div, i32* @kkkk, align 4
+ ret void
+}
+
+
Added: llvm/trunk/test/CodeGen/Mips/divu_remu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/divu_remu.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/divu_remu.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/divu_remu.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,23 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 103, align 4
+ at jjjj = global i32 4, align 4
+ at kkkk = common global i32 0, align 4
+ at llll = common global i32 0, align 4
+
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %div = udiv i32 %0, %1
+ store i32 %div, i32* @kkkk, align 4
+ %rem = urem i32 %0, %1
+; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mflo ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+ store i32 %rem, i32* @llll, align 4
+ ret void
+}
+
+
Added: llvm/trunk/test/CodeGen/Mips/rem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/rem.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/rem.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/rem.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,19 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 103, align 4
+ at jjjj = global i32 -4, align 4
+ at kkkk = common global i32 0, align 4
+
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %rem = srem i32 %0, %1
+; 16: div $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+ store i32 %rem, i32* @kkkk, align 4
+ ret void
+}
+
+
Added: llvm/trunk/test/CodeGen/Mips/remu.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/remu.ll?rev=165783&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/remu.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/remu.ll Thu Oct 11 21:01:09 2012
@@ -0,0 +1,18 @@
+; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+
+ at iiii = global i32 103, align 4
+ at jjjj = global i32 4, align 4
+ at kkkk = common global i32 0, align 4
+ at .str = private unnamed_addr constant [15 x i8] c"%u = %u %% %u\0A\00", align 1
+
+define void @test() nounwind {
+entry:
+ %0 = load i32* @iiii, align 4
+ %1 = load i32* @jjjj, align 4
+ %rem = urem i32 %0, %1
+; 16: divu $zero, ${{[0-9]+}}, ${{[0-9]+}}
+; 16: mfhi ${{[0-9]+}}
+ store i32 %rem, i32* @kkkk, align 4
+ ret void
+}
+
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