[llvm-commits] [llvm] r165604 - in /llvm/trunk/utils/TableGen: CodeGenSchedule.cpp CodeGenSchedule.h

[Andrew Trick]

Author: atrick
Date: Wed Oct 10 00:43:13 2012
New Revision: 165604

URL: http://llvm.org/viewvc/llvm-project?rev=165604&view=rev
Log:
TableGen subtarget emitter cleanup.

Consistently evaluate Aliases and Sequences recursively.

Modified:
    llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
    llvm/trunk/utils/TableGen/CodeGenSchedule.h

Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.cpp?rev=165604&r1=165603&r2=165604&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.cpp Wed Oct 10 00:43:13 2012
@@ -1449,50 +1449,57 @@
   }
 }
 
-
-// Collect resources for a set of read/write types and processor indices.
-void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
-                                            const IdxVec &Reads,
+void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
                                             const IdxVec &ProcIndices) {
-
-  for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
-    const CodeGenSchedRW &SchedRW = getSchedRW(*WI, /*IsRead=*/false);
-    if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
+  const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
+  if (SchedRW.TheDef) {
+    if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
       for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
            PI != PE; ++PI) {
         addWriteRes(SchedRW.TheDef, *PI);
       }
     }
-    for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
-         AI != AE; ++AI) {
-      const CodeGenSchedRW &AliasRW =
-        getSchedRW((*AI)->getValueAsDef("AliasRW"));
-      if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedWriteRes")) {
-        Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
-        addWriteRes(AliasRW.TheDef, getProcModel(ModelDef).Index);
-      }
-    }
-  }
-  for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI) {
-    const CodeGenSchedRW &SchedRW = getSchedRW(*RI, /*IsRead=*/true);
-    if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
+    else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
       for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
            PI != PE; ++PI) {
         addReadAdvance(SchedRW.TheDef, *PI);
       }
     }
-    for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
-         AI != AE; ++AI) {
-      const CodeGenSchedRW &AliasRW =
-        getSchedRW((*AI)->getValueAsDef("AliasRW"));
-      if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedReadAdvance")) {
-        Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
-        addReadAdvance(AliasRW.TheDef, getProcModel(ModelDef).Index);
-      }
+  }
+  for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
+       AI != AE; ++AI) {
+    IdxVec AliasProcIndices;
+    if ((*AI)->getValueInit("SchedModel")->isComplete()) {
+      AliasProcIndices.push_back(
+        getProcModel((*AI)->getValueAsDef("SchedModel")).Index);
+    }
+    else
+      AliasProcIndices = ProcIndices;
+    const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
+    assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
+
+    IdxVec ExpandedRWs;
+    expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
+    for (IdxIter SI = ExpandedRWs.begin(), SE = ExpandedRWs.end();
+         SI != SE; ++SI) {
+      collectRWResources(*SI, IsRead, AliasProcIndices);
     }
   }
 }
 
+// Collect resources for a set of read/write types and processor indices.
+void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
+                                            const IdxVec &Reads,
+                                            const IdxVec &ProcIndices) {
+
+  for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
+    collectRWResources(*WI, /*IsRead=*/false, ProcIndices);
+
+  for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
+    collectRWResources(*RI, /*IsRead=*/true, ProcIndices);
+}
+
+
 // Find the processor's resource units for this kind of resource.
 Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
                                              const CodeGenProcModel &PM) const {

Modified: llvm/trunk/utils/TableGen/CodeGenSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenSchedule.h?rev=165604&r1=165603&r2=165604&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenSchedule.h (original)
+++ llvm/trunk/utils/TableGen/CodeGenSchedule.h Wed Oct 10 00:43:13 2012
@@ -394,6 +394,9 @@
 
   void collectItinProcResources(Record *ItinClassDef);
 
+  void collectRWResources(unsigned RWIdx, bool IsRead,
+                          const IdxVec &ProcIndices);
+
   void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
                           const IdxVec &ProcIndices);