[llvm-commits] [llvm] r164751 - in /llvm/trunk: lib/Target/Mips/MipsDSPInstrFormats.td lib/Target/Mips/MipsDSPInstrInfo.td lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h test/CodeGen/Mips/dsp-r1.ll
Akira Hatanaka
ahatanaka at mips.com
Wed Sep 26 19:15:58 PDT 2012
Author: ahatanak
Date: Wed Sep 26 21:15:57 2012
New Revision: 164751
URL: http://llvm.org/viewvc/llvm-project?rev=164751&view=rev
Log:
MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos Field instruction.
Modified:
llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelLowering.h
llvm/trunk/test/CodeGen/Mips/dsp-r1.ll
Modified: llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td?rev=164751&r1=164750&r2=164751&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td Wed Sep 26 21:15:57 2012
@@ -103,3 +103,13 @@
let Inst{10-6} = op;
let Inst{5-0} = 0b111000;
}
+
+class BPOSGE32_FMT<bits<5> op> : DSPInst {
+ bits<16> offset;
+
+ let Opcode = REGIMM_OPCODE.V;
+
+ let Inst{25-21} = 0;
+ let Inst{20-16} = op;
+ let Inst{15-0} = offset;
+}
Modified: llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td?rev=164751&r1=164750&r2=164751&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td Wed Sep 26 21:15:57 2012
@@ -103,6 +103,7 @@
class MADDU_DSP_ENC : MULT_FMT<0b011100, 0b000001>;
class MSUB_DSP_ENC : MULT_FMT<0b011100, 0b000100>;
class MSUBU_DSP_ENC : MULT_FMT<0b011100, 0b000101>;
+class BPOSGE32_ENC : BPOSGE32_FMT<0b11100>;
class EXTP_ENC : EXTR_W_TY1_FMT<0b00010>;
class EXTPV_ENC : EXTR_W_TY1_FMT<0b00011>;
@@ -216,6 +217,23 @@
string AsmString = !strconcat(instr_asm, "\t$ac, $rs, $rt");
}
+class BPOSGE32_PSEUDO_DESC_BASE<SDPatternOperator OpNode, InstrItinClass itin> :
+ MipsPseudo<(outs CPURegs:$dst), (ins), "", [(set CPURegs:$dst, (OpNode))]> {
+ list<Register> Uses = [DSPCtrl];
+ bit usesCustomInserter = 1;
+}
+
+class BPOSGE32_DESC_BASE<string instr_asm, InstrItinClass itin> {
+ dag OutOperandList = (outs);
+ dag InOperandList = (ins brtarget:$offset);
+ string AsmString = !strconcat(instr_asm, "\t$offset");
+ InstrItinClass Itinerary = itin;
+ list<Register> Uses = [DSPCtrl];
+ bit isBranch = 1;
+ bit isTerminator = 1;
+ bit hasDelaySlot = 1;
+}
+
//===----------------------------------------------------------------------===//
// MIPS DSP Rev 1
//===----------------------------------------------------------------------===//
@@ -260,6 +278,9 @@
class MSUBU_DSP_DESC : MULT_DESC_BASE<"msubu">;
+// Misc
+class BPOSGE32_DESC : BPOSGE32_DESC_BASE<"bposge32", NoItinerary>;
+
// Extr
class EXTP_DESC : EXTR_W_TY1_R1_DESC_BASE<"extp", MipsEXTP, NoItinerary>;
@@ -320,6 +341,9 @@
class MULSA_W_PH_DESC : DPA_W_PH_DESC_BASE<"mulsa.w.ph">;
+// Pseudos.
+def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32, NoItinerary>;
+
// Instruction defs.
// MIPS DSP Rev 1
def MULSAQ_S_W_PH : MULSAQ_S_W_PH_ENC, MULSAQ_S_W_PH_DESC;
@@ -341,6 +365,7 @@
def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
+def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
def EXTP : EXTP_ENC, EXTP_DESC;
def EXTPV : EXTPV_ENC, EXTPV_DESC;
def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=164751&r1=164750&r2=164751&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Sep 26 21:15:57 2012
@@ -978,6 +978,70 @@
return BB;
}
*/
+
+MachineBasicBlock *
+MipsTargetLowering::EmitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
+ // $bb:
+ // bposge32_pseudo $vr0
+ // =>
+ // $bb:
+ // bposge32 $tbb
+ // $fbb:
+ // li $vr2, 0
+ // b $sink
+ // $tbb:
+ // li $vr1, 1
+ // $sink:
+ // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
+
+ MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
+ const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
+ const TargetRegisterClass *RC = &Mips::CPURegsRegClass;
+ DebugLoc DL = MI->getDebugLoc();
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB));
+ MachineFunction *F = BB->getParent();
+ MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
+ F->insert(It, FBB);
+ F->insert(It, TBB);
+ F->insert(It, Sink);
+
+ // Transfer the remainder of BB and its successor edges to Sink.
+ Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)),
+ BB->end());
+ Sink->transferSuccessorsAndUpdatePHIs(BB);
+
+ // Add successors.
+ BB->addSuccessor(FBB);
+ BB->addSuccessor(TBB);
+ FBB->addSuccessor(Sink);
+ TBB->addSuccessor(Sink);
+
+ // Insert the real bposge32 instruction to $BB.
+ BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
+
+ // Fill $FBB.
+ unsigned VR2 = RegInfo.createVirtualRegister(RC);
+ BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
+ .addReg(Mips::ZERO).addImm(0);
+ BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
+
+ // Fill $TBB.
+ unsigned VR1 = RegInfo.createVirtualRegister(RC);
+ BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
+ .addReg(Mips::ZERO).addImm(1);
+
+ // Insert phi function to $Sink.
+ BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
+ MI->getOperand(0).getReg())
+ .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
+
+ MI->eraseFromParent(); // The pseudo instruction is gone now.
+ return Sink;
+}
+
MachineBasicBlock *
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const {
@@ -1086,6 +1150,8 @@
case Mips::ATOMIC_CMP_SWAP_I64:
case Mips::ATOMIC_CMP_SWAP_I64_P8:
return EmitAtomicCmpSwap(MI, BB, 8);
+ case Mips::BPOSGE32_PSEUDO:
+ return EmitBPOSGE32(MI, BB);
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=164751&r1=164750&r2=164751&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Sep 26 21:15:57 2012
@@ -262,6 +262,8 @@
virtual unsigned getJumpTableEncoding() const;
+ MachineBasicBlock *EmitBPOSGE32(MachineInstr *MI,
+ MachineBasicBlock *BB) const;
MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
unsigned Size, unsigned BinOpcode, bool Nand = false) const;
MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI,
Modified: llvm/trunk/test/CodeGen/Mips/dsp-r1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/dsp-r1.ll?rev=164751&r1=164750&r2=164751&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/dsp-r1.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/dsp-r1.ll Wed Sep 26 21:15:57 2012
@@ -288,6 +288,16 @@
declare i64 @llvm.mips.mthlip(i64, i32) nounwind
+define i32 @test__builtin_mips_bposge321(i32 %i0) nounwind readonly {
+entry:
+; CHECK: bposge32
+
+ %0 = tail call i32 @llvm.mips.bposge32()
+ ret i32 %0
+}
+
+declare i32 @llvm.mips.bposge32() nounwind readonly
+
define i64 @test__builtin_mips_madd1(i32 %i0, i32, i64 %a0, i32 %a1, i32 %a2) nounwind readnone {
entry:
; CHECK: madd
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