[llvm-commits] [PATCH] Prevent the mixing of S and D registers for vsqrt/vdiv instructions on A15

[Jim Grosbach]

On Sep 25, 2012, at 7:25 AM, Tim Northover <t.p.northover at gmail.com> wrote:

> Hi all,
> 
>> The attached patch prevents the mixing of D and S registers for vsqrt/vdiv
>> instructions when using neonfp on A15. This is necessary since single
>> precision math instructions use D registers when using neonfp, and there
>> are no equivalent instructions for vsqrt and vdiv.
> 
> I've taken a look at the patch, and while the extra duplicated
> instruction to support this is rather a hack, I can't see any other
> way to enforce the allocation constraints in that pattern.
> 
> This is  probably a necessary evil.
> 

The duplicated instruction is a non-starter. We're working hard to get rid of CodeGenOnly definitions. The pattern should be representable in another way using the existing instruction definition.

That is, the instruction definitions represent exactly that, the instructions. That's completely orthogonal to using NEON for scalar floating point.

The register allocator should already be handling the necessary sub-register copies for instructions that need them. Nothing fancy should be necessary. Can you elaborate on the original problem?

-JIm