[llvm-commits] [llvm] r164204 - in /llvm/trunk: lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrSSE.td utils/TableGen/X86RecognizableInstr.cpp utils/TableGen/X86RecognizableInstr.h

[Craig Topper]

It just seemed weird to have two different ways of specifying the same
thing as some instructions couldn't be handled by the automatic code and
required the explicit tag. It's no more error prone than the other VEX
tags. But I'll go ahead and add a check in the disassembler table builder.
Best to do it there since it sees all instructions.

On Wednesday, September 19, 2012, Jan Sjodin wrote:

> Are we just trying to save time during emission or is there another reason
> for making something manual that used to be automatic? It is definitely
> more error prone (as your commit already indicates). Would it make sense to
> keep the code for DEBUG, so that it can assert if there is an inconsistency.
>
> - Jan
>
>
>   ------------------------------
> *From:* Craig Topper <craig.topper at gmail.com <javascript:_e({}, 'cvml',
> 'craig.topper at gmail.com');>>
> *To:* llvm-commits at cs.uiuc.edu <javascript:_e({}, 'cvml',
> 'llvm-commits at cs.uiuc.edu');>
> *Sent:* Wednesday, September 19, 2012 2:37 AM
> *Subject:* [llvm-commits] [llvm] r164204 - in /llvm/trunk:
> lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrSSE.td
> utils/TableGen/X86RecognizableInstr.cpp
> utils/TableGen/X86RecognizableInstr.h
>
> Author: ctopper
> Date: Wed Sep 19 01:37:45 2012
> New Revision: 164204
>
> URL: http://llvm.org/viewvc/llvm-project?rev=164204&view=rev
> Log:
> Remove code for setting the VEX L-bit as a function of operand size from
> the code emitters and the disassembler table builder. Fix a couple
> instructions that were still missing VEX_L.
>
> Modified:
>     llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
>     llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
>     llvm/trunk/lib/Target/X86/X86InstrSSE.td
>     llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
>     llvm/trunk/utils/TableGen/X86RecognizableInstr.h
>
> Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp?rev=164204&r1=164203&r2=164204&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp Wed Sep 19
> 01:37:45 2012
> @@ -560,15 +560,6 @@
>   }
>
>
> -  // Set the vector length to 256-bit if YMM0-YMM15 is used
> -  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
> -    if (!MI.getOperand(i).isReg())
> -      continue;
> -    unsigned SrcReg = MI.getOperand(i).getReg();
> -    if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
> -      VEX_L = 1;
> -  }
> -
>   // Classify VEX_B, VEX_4V, VEX_R, VEX_X
>   unsigned NumOps = Desc.getNumOperands();
>   unsigned CurOp = 0;
>
> Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=164204&r1=164203&r2=164204&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Wed Sep 19 01:37:45 2012
> @@ -921,17 +921,6 @@
>   }
>
>
> -  // Set the vector length to 256-bit if YMM0-YMM15 is used
> -  for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
> -    if (!MI.getOperand(i).isReg())
> -      continue;
> -    if (MI.getOperand(i).isImplicit())
> -      continue;
> -    unsigned SrcReg = MI.getOperand(i).getReg();
> -    if (SrcReg >= X86::YMM0 && SrcReg <= X86::YMM15)
> -      VEX_L = 1;
> -  }
> -
>   // Classify VEX_B, VEX_4V, VEX_R, VEX_X
>   unsigned NumOps = Desc->getNumOperands();
>   unsigned CurOp = 0;
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=164204&r1=164203&r2=164204&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Sep 19 01:37:45 2012
> @@ -2614,11 +2614,11 @@
>               OpSize, VEX;
>   def VMOVMSKPSYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins
> VR256:$src),
>               "movmskps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
> -            SSEPackedSingle>, TB, VEX;
> +            SSEPackedSingle>, TB, VEX, VEX_L;
>   def VMOVMSKPDYr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins
> VR256:$src),
>               "movmskpd\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK,
>               SSEPackedDouble>, TB,
> -            OpSize, VEX;
> +            OpSize, VEX, VEX_L;
> }
>
> defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
> "movmskps",
>
> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=164204&r1=164203&r2=164204&view=diff
>
> ==============================================================================
> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
>
>

-- 
~Craig
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