[llvm-commits] [llvm] r164092 - in /llvm/trunk: include/llvm/MC/MCSchedule.h include/llvm/MC/MCSubtargetInfo.h include/llvm/Target/TargetSubtargetInfo.h lib/MC/MCSubtargetInfo.cpp lib/Target/ARM/ARMSubtarget.cpp utils/TableGen/SubtargetEmitter.cpp
Andrew Trick
atrick at apple.com
Mon Sep 17 20:18:56 PDT 2012
Author: atrick
Date: Mon Sep 17 22:18:56 2012
New Revision: 164092
URL: http://llvm.org/viewvc/llvm-project?rev=164092&view=rev
Log:
TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.
Modified:
llvm/trunk/include/llvm/MC/MCSchedule.h
llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
llvm/trunk/lib/MC/MCSubtargetInfo.cpp
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCSchedule.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSchedule.h?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSchedule.h (original)
+++ llvm/trunk/include/llvm/MC/MCSchedule.h Mon Sep 17 22:18:56 2012
@@ -172,10 +172,8 @@
unsigned ProcID;
const MCProcResourceDesc *ProcResourceTable;
const MCSchedClassDesc *SchedClassTable;
-#ifndef NDEBUG
unsigned NumProcResourceKinds;
unsigned NumSchedClasses;
-#endif
// Instruction itinerary tables used by InstrItineraryData.
friend class InstrItineraryData;
const InstrItinerary *InstrItineraries;
@@ -190,14 +188,22 @@
LoadLatency(DefaultLoadLatency),
HighLatency(DefaultHighLatency),
MispredictPenalty(DefaultMispredictPenalty),
- ProcID(0), InstrItineraries(0) {}
+ ProcID(0), ProcResourceTable(0), SchedClassTable(0),
+ NumProcResourceKinds(0), NumSchedClasses(0),
+ InstrItineraries(0) {
+ (void)NumProcResourceKinds;
+ (void)NumSchedClasses;
+ }
// Table-gen driven ctor.
MCSchedModel(unsigned iw, int ml, unsigned ll, unsigned hl, unsigned mp,
+ unsigned pi, const MCProcResourceDesc *pr,
+ const MCSchedClassDesc *sc, unsigned npr, unsigned nsc,
const InstrItinerary *ii):
IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl),
- MispredictPenalty(mp), ProcID(0), ProcResourceTable(0),
- SchedClassTable(0), InstrItineraries(ii) {}
+ MispredictPenalty(mp), ProcID(pi), ProcResourceTable(pr),
+ SchedClassTable(sc), NumProcResourceKinds(npr), NumSchedClasses(nsc),
+ InstrItineraries(ii) {}
unsigned getProcessorID() const { return ProcID; }
Modified: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Mon Sep 17 22:18:56 2012
@@ -36,6 +36,7 @@
const MCWriteProcResEntry *WriteProcResTable;
const MCWriteLatencyEntry *WriteLatencyTable;
const MCReadAdvanceEntry *ReadAdvanceTable;
+ const MCSchedModel *CPUSchedModel;
const InstrStage *Stages; // Instruction itinerary stages
const unsigned *OperandCycles; // Itinerary operand cycles
@@ -49,6 +50,9 @@
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC, const unsigned *FP,
unsigned NF, unsigned NP);
@@ -80,6 +84,10 @@
///
const MCSchedModel *getSchedModelForCPU(StringRef CPU) const;
+ /// getSchedModel - Get the machine model for this subtarget's CPU.
+ ///
+ const MCSchedModel *getSchedModel() const { return CPUSchedModel; }
+
/// Return an iterator at the first process resource consumed by the given
/// scheduling class.
const MCWriteProcResEntry *getWriteProcResBegin(
Modified: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Mon Sep 17 22:18:56 2012
@@ -14,6 +14,7 @@
#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
#define LLVM_TARGET_TARGETSUBTARGETINFO_H
+#include "llvm/CodeGen/TargetSchedule.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/CodeGen.h"
@@ -43,6 +44,15 @@
virtual ~TargetSubtargetInfo();
+ /// Initialize a copy of the scheduling model for this subtarget.
+ /// TargetSchedModel provides the interface for the subtarget's
+ /// instruction scheduling information.
+ void initSchedModel(TargetSchedModel &SchedModel,
+ const TargetInstrInfo *TII) const {
+ // getSchedModel returns the static MCSchedModel initialized by InitMCSubtargetInfo.
+ SchedModel.init(*getSchedModel(), this, TII);
+ }
+
/// getSpecialAddressLatency - For targets where it is beneficial to
/// backschedule instructions that compute addresses, return a value
/// indicating the number of scheduling cycles of backscheduling that
Modified: llvm/trunk/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Mon Sep 17 22:18:56 2012
@@ -24,6 +24,9 @@
const SubtargetFeatureKV *PF,
const SubtargetFeatureKV *PD,
const SubtargetInfoKV *ProcSched,
+ const MCWriteProcResEntry *WPR,
+ const MCWriteLatencyEntry *WL,
+ const MCReadAdvanceEntry *RA,
const InstrStage *IS,
const unsigned *OC,
const unsigned *FP,
@@ -32,6 +35,10 @@
ProcFeatures = PF;
ProcDesc = PD;
ProcSchedModels = ProcSched;
+ WriteProcResTable = WPR;
+ WriteLatencyTable = WL;
+ ReadAdvanceTable = RA;
+
Stages = IS;
OperandCycles = OC;
ForwardingPaths = FP;
@@ -41,8 +48,9 @@
SubtargetFeatures Features(FS);
FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
ProcFeatures, NumFeatures);
-}
+ CPUSchedModel = getSchedModelForCPU(CPU);
+}
/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
/// feature string) and recompute feature bits.
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon Sep 17 22:18:56 2012
@@ -13,8 +13,9 @@
#include "ARMSubtarget.h"
#include "ARMBaseRegisterInfo.h"
+#include "ARMBaseInstrInfo.h"
#include "llvm/GlobalValue.h"
-#include "llvm/Target/TargetSubtargetInfo.h"
+#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#define GET_SUBTARGETINFO_TARGET_DESC
Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=164092&r1=164091&r2=164092&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Mon Sep 17 22:18:56 2012
@@ -708,6 +708,7 @@
SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
SCTab.resize(SCTab.size() + 1);
MCSchedClassDesc &SCDesc = SCTab.back();
+ // SCDesc.Name is guarded by NDEBUG
SCDesc.NumMicroOps = 0;
SCDesc.BeginGroup = false;
SCDesc.EndGroup = false;
@@ -1018,6 +1019,15 @@
EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
+ OS << " " << PI->Index << ", // Processor ID\n";
+ if (PI->hasInstrSchedModel())
+ OS << " " << PI->ModelName << "ProcResources" << ",\n"
+ << " " << PI->ModelName << "SchedClasses" << ",\n"
+ << " " << PI->ProcResourceDefs.size()+1 << ",\n"
+ << " " << (SchedModels.schedClassEnd()
+ - SchedModels.schedClassBegin()) << ",\n";
+ else
+ OS << " 0, 0, 0, 0, // No instruction-level machine model.\n";
if (SchedModels.hasItineraryClasses())
OS << " " << PI->ItinsDef->getName() << ");\n";
else
@@ -1191,13 +1201,17 @@
else
OS << "0, ";
OS << '\n'; OS.indent(22);
+ OS << Target << "ProcSchedKV, "
+ << Target << "WriteProcResTable, "
+ << Target << "WriteLatencyTable, "
+ << Target << "ReadAdvanceTable, ";
if (SchedModels.hasItineraryClasses()) {
- OS << Target << "ProcSchedKV, "
- << Target << "Stages, "
+ OS << '\n'; OS.indent(22);
+ OS << Target << "Stages, "
<< Target << "OperandCycles, "
<< Target << "ForwardingPaths, ";
} else
- OS << "0, 0, 0, 0, ";
+ OS << "0, 0, 0, ";
OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
OS << "} // End llvm namespace \n";
@@ -1263,13 +1277,18 @@
OS << Target << "SubTypeKV, ";
else
OS << "0, ";
+ OS << '\n'; OS.indent(22);
+ OS << Target << "ProcSchedKV, "
+ << Target << "WriteProcResTable, "
+ << Target << "WriteLatencyTable, "
+ << Target << "ReadAdvanceTable, ";
+ OS << '\n'; OS.indent(22);
if (SchedModels.hasItineraryClasses()) {
- OS << Target << "ProcSchedKV, "
- << Target << "Stages, "
+ OS << Target << "Stages, "
<< Target << "OperandCycles, "
<< Target << "ForwardingPaths, ";
} else
- OS << "0, 0, 0, 0, ";
+ OS << "0, 0, 0, ";
OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
OS << "} // End llvm namespace \n";
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