[llvm-commits] Fixing Bug 13662: paired register for inline asm with 64-bit data on ARM

[Weiming Zhao]

Ping.

 

From: Weiming Zhao [mailto:weimingz at codeaurora.org] 
Sent: Wednesday, September 12, 2012 10:21 AM
To: llvm-commits at cs.uiuc.edu
Subject: Fixing Bug 13662: paired register for inline asm with 64-bit data
on ARM

 

Hi,

 

Attached is the patch for fixing the long long data passing to inline asm
for ARM.

 

Since current LLVM has no support for paired GPR reg class for 64-bit data,
we follow the same practice as ldrexd/strexd instincs
(ARMTargetLowering::EmitAtomicBinary64).  That is, we hard code the physical
registers.

 

However, since inline asm may has some physical registers specified by
programmers, we cannot simply hard code R2/R3 as those intrincs do.

So, we have to add a variable "AssignedPhyRegs" to track those already
specified physical regs of that inline ASM and thus avoid them during
assigning.

 

Please help to review the patch.

 

Thanks,

Weiming

 

 

 

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by
The Linux Foundation

 

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