[llvm-commits] [llvm] r164030 - in /llvm/trunk: lib/Target/ARM/ARM.td test/CodeGen/ARM/a15-mla.ll

Silviu Baranga silviu.baranga at arm.com
Mon Sep 17 07:10:54 PDT 2012


Author: sbaranga
Date: Mon Sep 17 09:10:54 2012
New Revision: 164030

URL: http://llvm.org/viewvc/llvm-project?rev=164030&view=rev
Log:
Removed the VMLxForwarding feature for the Cortex-A15 target.

Added:
    llvm/trunk/test/CodeGen/ARM/a15-mla.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARM.td

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=164030&r1=164029&r2=164030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon Sep 17 09:10:54 2012
@@ -142,8 +142,7 @@
 // FIXME: It has not been determined if A15 has these features.
 def ProcA15      : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
                                    "Cortex-A15 ARM processors",
-                                   [FeatureVMLxForwarding,
-                                    FeatureT2XtPk, FeatureFP16,
+                                   [FeatureT2XtPk, FeatureFP16,
                                     FeatureAvoidPartialCPSR]>;
 
 class ProcNoItin<string Name, list<SubtargetFeature> Features>

Added: llvm/trunk/test/CodeGen/ARM/a15-mla.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/a15-mla.ll?rev=164030&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/a15-mla.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/a15-mla.ll Mon Sep 17 09:10:54 2012
@@ -0,0 +1,12 @@
+; RUN: llc < %s  -march=arm -float-abi=hard -mcpu=cortex-a15 -mattr=+neon,+neonfp | FileCheck %s
+
+; This test checks that the VMLxForwarting feature is disabled for A15.
+; CHECK: fun_a
+define <4 x i32> @fun_a(<4 x i32> %x, <4 x i32> %y) nounwind{
+  %1 = add <4 x i32> %x, %y
+; CHECK-NOT: vmul
+; CHECK: vmla
+  %2 = mul <4 x i32> %1, %1
+  %3 = add <4 x i32> %y, %2
+  ret <4 x i32> %3
+}





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