[llvm-commits] [llvm] r163753 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

[Bill Wendling]

On Sep 12, 2012, at 4:27 PM, Akira Hatanaka <ahatanaka at mips.com> wrote:

> Author: ahatanak
> Date: Wed Sep 12 18:27:55 2012
> New Revision: 163753
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=163753&view=rev
> Log:
> Misc.
> 1. Remove RA from list of allocatable registers
> 2. Enable d,y,r constraint inline assembly instructions
> 
> Patch by Reed Kotler.
> 
Thanks for applying the patch. In future though, separate patches which have nothing to do with each other into two commits. :-)

-bw

> 
> Modified:
>    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=163753&r1=163752&r2=163753&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Sep 12 18:27:55 2012
> @@ -113,7 +113,6 @@
> 
>   if (Subtarget->inMips16Mode()) {
>     addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
> -    addRegisterClass(MVT::i32, &Mips::CPURARegRegClass);
>   }
> 
>   if (!TM.Options.UseSoftFloat) {
> @@ -1571,7 +1570,8 @@
>   if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) {
>     SDVTList VTs = DAG.getVTList(MVT::i32);
> 
> -    const MipsTargetObjectFile &TLOF = (const MipsTargetObjectFile&)getObjFileLowering();
> +    const MipsTargetObjectFile &TLOF =
> +      (const MipsTargetObjectFile&)getObjFileLowering();
> 
>     // %gp_rel relocation
>     if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
> @@ -3325,8 +3325,11 @@
>     case 'd': // Address register. Same as 'r' unless generating MIPS16 code.
>     case 'y': // Same as 'r'. Exists for compatibility.
>     case 'r':
> -      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
> +      if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) {
> +        if (Subtarget->inMips16Mode())
> +          return std::make_pair(0U, &Mips::CPU16RegsRegClass);
>         return std::make_pair(0U, &Mips::CPURegsRegClass);
> +      }
>       if (VT == MVT::i64 && !HasMips64)
>         return std::make_pair(0U, &Mips::CPURegsRegClass);
>       if (VT == MVT::i64 && HasMips64)
> 
> 
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