[llvm-commits] [llvm] r163628 - in /llvm/trunk: include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h lib/MC/MCRegisterInfo.cpp utils/TableGen/RegisterInfoEmitter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Tue Sep 11 09:34:02 PDT 2012
Author: stoklund
Date: Tue Sep 11 11:34:02 2012
New Revision: 163628
URL: http://llvm.org/viewvc/llvm-project?rev=163628&view=rev
Log:
Add MCRI::getNumSubRegIndices() and start checking SubRegIndex ranges.
Apparently, NumSubRegIndices was completely unused before. Adjust it by
one to include the null subreg index, just like getNumRegs() includes
the null register.
Modified:
llvm/trunk/include/llvm/MC/MCRegisterInfo.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/MC/MCRegisterInfo.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=163628&r1=163627&r2=163628&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Tue Sep 11 11:34:02 2012
@@ -333,6 +333,13 @@
return NumRegs;
}
+ /// getNumSubRegIndices - Return the number of sub-register indices
+ /// understood by the target. Index 0 is reserved for the no-op sub-register,
+ /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
+ unsigned getNumSubRegIndices() const {
+ return NumSubRegIndices;
+ }
+
/// getNumRegUnits - Return the number of (native) register units in the
/// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
/// can be accessed through MCRegUnitIterator defined below.
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=163628&r1=163627&r2=163628&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Sep 11 11:34:02 2012
@@ -327,7 +327,8 @@
/// getSubRegIndexName - Return the human-readable symbolic target-specific
/// name for the specified SubRegIndex.
const char *getSubRegIndexName(unsigned SubIdx) const {
- assert(SubIdx && "This is not a subregister index");
+ assert(SubIdx && SubIdx < getNumSubRegIndices() &&
+ "This is not a subregister index");
return SubRegIndexNames[SubIdx-1];
}
Modified: llvm/trunk/lib/MC/MCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCRegisterInfo.cpp?rev=163628&r1=163627&r2=163628&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/MC/MCRegisterInfo.cpp Tue Sep 11 11:34:02 2012
@@ -24,6 +24,8 @@
}
unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const {
+ assert(Idx && Idx < getNumSubRegIndices() &&
+ "This is not a subregister index");
// Get a pointer to the corresponding SubRegIndices list. This list has the
// name of each sub-register in the same order as MCSubRegIterator.
const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
@@ -34,6 +36,7 @@
}
unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
+ assert(SubReg && SubReg < getNumRegs() && "This is not a register");
// Get a pointer to the corresponding SubRegIndices list. This list has the
// name of each sub-register in the same order as MCSubRegIterator.
const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=163628&r1=163627&r2=163628&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Sep 11 11:34:02 2012
@@ -770,7 +770,7 @@
<< TargetName << "RegDiffLists, "
<< TargetName << "RegStrings, "
<< TargetName << "SubRegIdxLists, "
- << SubRegIndices.size() << ",\n"
+ << (SubRegIndices.size() + 1) << ",\n"
<< " " << TargetName << "RegEncodingTable);\n\n";
EmitRegMapping(OS, Regs, false);
@@ -1131,7 +1131,7 @@
<< " " << TargetName << "RegDiffLists,\n"
<< " " << TargetName << "RegStrings,\n"
<< " " << TargetName << "SubRegIdxLists,\n"
- << " " << SubRegIndices.size() << ",\n"
+ << " " << SubRegIndices.size() + 1 << ",\n"
<< " " << TargetName << "RegEncodingTable);\n\n";
EmitRegMapping(OS, Regs, true);
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