[llvm-commits] [PATCH 1/2] Improve optimization to fold base update into LDM/STM
David Peixotto
dpeixott at codeaurora.org
Sat Sep 8 14:19:02 PDT 2012
A reviewer of the second patch in this patch set suggested running tests
with -verify-machineinstrs. The verifier found a few issues, which have been
corrected in this updated patch.
Please review this updated patch.
Thanks,
Dave
-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
by The Linux Foundation
> -----Original Message-----
> From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-
> bounces at cs.uiuc.edu] On Behalf Of David Peixotto
> Sent: Friday, August 31, 2012 11:03 AM
> To: llvm-commits at cs.uiuc.edu
> Subject: [llvm-commits] [PATCH 1/2] Improve optimization to fold base
> update into LDM/STM
>
> Please review the attached patch. Thanks!
>
> The base updated optimization for LDM/STM tries to fold an update of the
> base address register into the instruction itself. For example,
>
> LDM R0, {R1, R2}
> ADD R0, R0, #8
> ==>
> LDM R0!, {R1, R2}
>
> This commit improves the existing optimization in the following ways:
>
> 1. Try to optimize all LDM/STM instructions -- previously we only
> transformed LDM/STM instructions that were created by grouping
> multiple
> LDR/STR instructions together in an earlier phase of the
optimization.
> 2. Try to merge with instruction any distance away -- previously we only
> merged with an instruction directly preceeding or following the
LDM/STM.
> 3. Add support for optimizing VLDM/VSTM.
>
> The new support for folding the base update into vector memory ops include
> the following instructions:
>
> VLDM == VLDMIA
> VSTM == VSTMIA
>
> We can fold the base address update into vector loads/stores that access
> 1 singleword register, 1 doubleword register, or 2 doubleword registers.
>
> In order to enable the optimization for 2 doubleword registers I also
added
> new pseudo instructions for VLDM/VSTM with update.
>
> The new pseudo instructions are for the VLDMQ and VSTMQ instructions
> that modify the base register. We can use these instructions to generate
the
> VLDM and VSTM instructions that write back to the base register. For
> example,
>
> vldm R0!, {D0, D1}
> vstm R0!, {D0, D1}
>
>
>
> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> hosted by The Linux Foundation
>
>
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