[llvm-commits] [llvm] r163396 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Sep  7 12:34:15 2012
New Revision: 163396

URL: http://llvm.org/viewvc/llvm-project?rev=163396&view=rev
Log:
Custom DAGCombine for and/or/xor are for all ARMs.

The 'select' transformations apply to all ARM architectures and don't
require hasV6T2Ops.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=163396&r1=163395&r2=163396&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Sep  7 12:34:15 2012
@@ -796,12 +796,9 @@
   setTargetDAGCombine(ISD::ADD);
   setTargetDAGCombine(ISD::SUB);
   setTargetDAGCombine(ISD::MUL);
-
-  if (Subtarget->hasV6T2Ops() || Subtarget->hasNEON()) {
-    setTargetDAGCombine(ISD::AND);
-    setTargetDAGCombine(ISD::OR);
-    setTargetDAGCombine(ISD::XOR);
-  }
+  setTargetDAGCombine(ISD::AND);
+  setTargetDAGCombine(ISD::OR);
+  setTargetDAGCombine(ISD::XOR);
 
   if (Subtarget->hasV6Ops())
     setTargetDAGCombine(ISD::SRL);