[llvm-commits] [PATCH] add boolean simplification support for RDRAND intrinsics
Craig Topper
craig.topper at gmail.com
Wed Sep 5 23:03:10 PDT 2012
This change seems unrelated as its floating point related and rdrand is
integer.
@@ -14165,22 +14195,6 @@ static SDValue checkFlaggedOrCombine(SDValue Or,
X86::CondCode &CC,
return DAG.getNode(X86ISD::PTEST, DL, MVT::i32, VecIn, VecIn);
}
-static bool isValidFCMOVCondition(X86::CondCode CC) {
- switch (CC) {
- default:
- return false;
- case X86::COND_B:
- case X86::COND_BE:
- case X86::COND_E:
- case X86::COND_P:
- case X86::COND_AE:
- case X86::COND_A:
- case X86::COND_NE:
- case X86::COND_NP:
- return true;
- }
-}
-
/// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL]
static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
@@ -14212,7 +14226,7 @@ static SDValue PerformCMOVCombine(SDNode *N,
SelectionDAG &DAG,
Flags = checkBoolTestSetCCCombine(Cond, CC);
if (Flags.getNode() &&
// Extra check as FCMOV only supports a subset of X86 cond.
- (FalseOp.getValueType() != MVT::f80 || isValidFCMOVCondition(CC))) {
+ (FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {
SDValue Ops[] = { FalseOp, TrueOp,
DAG.getConstant(CC, MVT::i8), Flags };
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(),
On Wed, Sep 5, 2012 at 3:01 PM, Michael Liao <michael.liao at intel.com> wrote:
> Ping.
>
> Thanks for review
> - Michael
>
> On Tue, 2012-08-28 at 00:12 -0700, Michael Liao wrote:
> > Hi
> >
> > The attached patch adds the boolean simplification support for RDRAND
> > intrinsics which, following GCC approach, generate its boolean result by
> > CMOV instead of SETCC. In addition, this patch cleans up the redundant
> > code previously added.
> >
> > Thanks for your review.
> >
> > Yours
> > - Michael
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
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> llvm-commits mailing list
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>
--
~Craig
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