[llvm-commits] [llvm] r162968 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/atomic-op.ll

[Jim Grosbach]

I suspect those weren't typos, but holdovers predating the existence of the rGPR register class and back when adding new register classes was expensive. We'd sometimes use tGPR as a shorthand to preclude the upper regs like SP and LR. Pretty horrible, and things like rGPR are much, much better.

-j
On Aug 30, 2012, at 7:08 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:

> Author: stoklund
> Date: Thu Aug 30 21:08:34 2012
> New Revision: 162968
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=162968&view=rev
> Log:
> Fix a couple of typos in EmitAtomic.
> 
> Thumb2 instructions are mostly constrained to rGPR, not tGPR which is
> for Thumb1.
> 
> rdar://problem/12203728
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/test/CodeGen/ARM/atomic-op.ll
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=162968&r1=162967&r2=162968&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Aug 30 21:08:34 2012
> @@ -5418,7 +5418,7 @@
>   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
> 
>   const TargetRegisterClass *TRC = isThumb2 ?
> -    (const TargetRegisterClass*)&ARM::tGPRRegClass :
> +    (const TargetRegisterClass*)&ARM::rGPRRegClass :
>     (const TargetRegisterClass*)&ARM::GPRRegClass;
>   unsigned scratch = MRI.createVirtualRegister(TRC);
>   unsigned scratch2 = (!BinOpcode) ? incr : MRI.createVirtualRegister(TRC);
> @@ -5529,7 +5529,7 @@
>   exitMBB->transferSuccessorsAndUpdatePHIs(BB);
> 
>   const TargetRegisterClass *TRC = isThumb2 ?
> -    (const TargetRegisterClass*)&ARM::tGPRRegClass :
> +    (const TargetRegisterClass*)&ARM::rGPRRegClass :
>     (const TargetRegisterClass*)&ARM::GPRRegClass;
>   unsigned scratch = MRI.createVirtualRegister(TRC);
>   unsigned scratch2 = MRI.createVirtualRegister(TRC);
> 
> Modified: llvm/trunk/test/CodeGen/ARM/atomic-op.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/atomic-op.ll?rev=162968&r1=162967&r2=162968&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/atomic-op.ll (original)
> +++ llvm/trunk/test/CodeGen/ARM/atomic-op.ll Thu Aug 30 21:08:34 2012
> @@ -159,3 +159,13 @@
>   store i8 %3, i8* %old
>   ret void
> }
> +
> +; CHECK: func4
> +; This function should not need to use callee-saved registers.
> +; rdar://problem/12203728
> +; CHECK-NOT: r4
> +define i32 @func4(i32* %p) nounwind optsize ssp {
> +entry:
> +  %0 = atomicrmw add i32* %p, i32 1 monotonic
> +  ret i32 %0
> +}
> 
> 
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