[llvm-commits] [patch] Enable the generation of vaddl-type instructions from extloads on ARM

[Silviu Baranga]

Hi,

Currently LLVM will not generate a vaddl-type instructions when an extload
node is in the input dag. All vector extload nodes are implemented with
a load instruction and a lengthening instruction on ARM. If the lengthening
instruction is followed by an add instruction, it would be better to
generate
a vaddl-type instruction instead.

To do this, we split all lengthening dag nodes which extend a type to more
then twice its size (this is OK because these nodes would be implemented by
multiple instructions anyway) into two lengthening nodes. One node will be
later
combined to form the extload node, and the other can be selected as part of
a
vaddl-type instruction (there are already patterns for this).

To stop the dag nodes from re-combining, we insert a BREAK node between
them. The
BREAK node is used as an optimization barrier for the DAG combiner, and
might be 
useful in other cases as well. We remove the BREAK node in the instruction 
selection stage.

This approach allows the reuse of existing selection patterns.

This patch depends on the following other patch:
http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20120827/149201.
html

Please review!

Thanks,
Silviu
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