[llvm-commits] [PATCH] Improve vmov domain conversion (followup)

[James Molloy]

Hi,

This patch follows on from the work Tim did recently on improving
execution domain support for VMOV and VLDR.

As part of that patch, Jakob noticed a problem:


> Unfortunately, there is a more serious problem with these transforms
> that I missed earlier; they break data dependencies in the other lane.
> This could lead to miscompilations when the late scheduler reorders
> instructions.
> 
> Consider this code:
> 
>   %s1<def> = foo
>   %s0<def> = vldrs ...
>   bar %s1
> 
> There is a read-after-write data dependency between foo and bar
> through %s0. Now transform vldrs:
> 
>   %s1<def> = foo
>   %d0<def> = vld1ln ..., %d0<undef>
>   bar %s1
> 
> The wider def establishes a dependency between vld1ln and bar, which
> is OK, but the %d0<undef> severs the data dependency from foo. That is
> the meaning of the <undef> flag.
> 
> Without the dependency, there is nothing stopping the scheduler from
> moving foo below bar.
> 
> A %s1<imp-use> operand can be used to establish a dependency between
> foo and vld1ln:
> 
>   %s1<def> = foo
>   %d0<def> = vld1ln ..., %d0<undef>, %s1<imp-use>
>   bar %s1
> 
> This will insert vld1ln in the dependency chain between foo and bar
> without breaking it.
> 
> You can't add a dependency on a value that isn't there, so you need to
> know that %s1 is live before you can add the <imp-use> operand.
> 
Tim fixed this by guarding against it. Unfortunately that didn't fix our
use-case, so I attach a patch to fix it completely.

It defines a generic "isRegisterLive()" function that takes a
MachineInstr and register and will check if the register is live at
arrival at the MachineInstr.

It is O(N). :( . I couldn't see a better way of doing it though.

Could you please review?

Cheers,

James
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