[llvm-commits] [llvm] r163086 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp test/CodeGen/ARM/2012-08-30-select.ll

[Nadav Rotem]

Author: nadav
Date: Sun Sep  2 03:20:07 2012
New Revision: 163086

URL: http://llvm.org/viewvc/llvm-project?rev=163086&view=rev
Log:
Generate better select code by allowing the target to use scalar select, and not sign-extend.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
    llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=163086&r1=163085&r2=163086&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Sun Sep  2 03:20:07 2012
@@ -475,10 +475,9 @@
   // What is the size of each element in the vector mask.
   EVT BitTy = MaskTy.getScalarType();
 
-  // Turn the mask into an all-one or all-zero word.
-  Mask = DAG.getAnyExtOrTrunc(Mask, DL, BitTy);
-  Mask = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, BitTy, Mask,
-                     DAG.getValueType(MVT::i1));
+  Mask = DAG.getNode(ISD::SELECT, DL, BitTy, Mask,
+          DAG.getConstant(APInt::getAllOnesValue(BitTy.getSizeInBits()), BitTy),
+          DAG.getConstant(3, BitTy));
 
   // Broadcast the mask so that the entire vector is all-one or all zero.
   SmallVector<SDValue, 8> Ops(NumElem, Mask);

Modified: llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll?rev=163086&r1=163085&r2=163086&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2012-08-30-select.ll Sun Sep  2 03:20:07 2012
@@ -2,6 +2,8 @@
 ; rdar://12201387
 
 ;CHECK: select_s_v_v
+;CHECK: it  eq
+;CHECK-NEXT: moveq.w r2, #-1
 ;CHECK: vbsl
 ;CHECK: bx
 define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) {