[llvm-commits] [llvm] r163040 - /llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll
Manman Ren
mren at apple.com
Fri Aug 31 17:17:06 PDT 2012
Author: mren
Date: Fri Aug 31 19:17:06 2012
New Revision: 163040
URL: http://llvm.org/viewvc/llvm-project?rev=163040&view=rev
Log:
Fix Atom bots for r163036.
Modified:
llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll
Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll?rev=163040&r1=163039&r2=163040&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-26.ll Fri Aug 31 19:17:06 2012
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=x86 -mattr=sse41 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=generic -mattr=sse41 | FileCheck %s
+; RUN: llc < %s -march=x86 -mcpu=atom -mattr=+sse41 | FileCheck -check-prefix=ATOM %s
; Transpose example using the more generic vector shuffle. Return float8
; instead of float16
@@ -17,6 +18,12 @@
; CHECK: unpckhps
; CHECK: unpcklps
; CHECK: unpckhps
+; Different instruction order for Atom.
+; ATOM: transpose2
+; ATOM: unpckhps
+; ATOM: unpckhps
+; ATOM: unpckhps
+; ATOM: unpcklps
%unpcklps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
%unpckhps = shufflevector <4 x float> %p0, <4 x float> %p2, <4 x i32> < i32 2, i32 6, i32 3, i32 7 > ; <<4 x float>> [#uses=2]
%unpcklps8 = shufflevector <4 x float> %p1, <4 x float> %p3, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x float>> [#uses=2]
@@ -38,6 +45,10 @@
; CHECK: movhps ([[BASEREG:%[a-z]+]]),
; CHECK: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
; CHECK: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
+; ATOM: lo_hi_shift
+; ATOM: movhps ([[BASEREG:%[a-z]+]]),
+; ATOM: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
+; ATOM: extractps ${{[0-9]+}}, %xmm{{[0-9]+}}, {{[0-9]*}}([[BASEREG]])
%v.i = bitcast float* %y to <4 x float>*
%0 = load <4 x float>* %v.i, align 1
%1 = bitcast float* %x to <1 x i64>*
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