[llvm-commits] [llvm] r162916 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

[NAKAMURA Takumi]

Author: chapuni
Date: Thu Aug 30 10:52:29 2012
New Revision: 162916

URL: http://llvm.org/viewvc/llvm-project?rev=162916&view=rev
Log:
PPCISelLowering.cpp: Fix r162725.

[Tobias von Koch] What's happening here is that the CR6SET/CR6UNSET is breaking the chain of register copies glued to the function call (BL_SVR4 node). The scheduler then moves other instructions in between those and the function call, which isn't good!

Right. That's the case where there is no chain of register copies before the call, so InFlag == 0... Attached is a new revision of the patch which should fix this for good.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=162916&r1=162915&r2=162916&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Aug 30 10:52:29 2012
@@ -3164,8 +3164,12 @@
   // Set CR bit 6 to true if this is a vararg call with floating args passed in
   // registers.
   if (isVarArg) {
+    SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
+    SDValue Ops[] = { Chain, InFlag };
+
     Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
-                        dl, DAG.getVTList(MVT::Other, MVT::Glue), Chain);
+                        dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
+
     InFlag = Chain.getValue(1);
   }