[llvm-commits] [llvm] r162703 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
Bill Wendling
isanbard at gmail.com
Mon Aug 27 15:12:45 PDT 2012
Author: void
Date: Mon Aug 27 17:12:44 2012
New Revision: 162703
URL: http://llvm.org/viewvc/llvm-project?rev=162703&view=rev
Log:
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>
Added:
llvm/trunk/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
Modified:
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=162703&r1=162702&r2=162703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Mon Aug 27 17:12:44 2012
@@ -712,11 +712,12 @@
unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
assert(Dst && Src && "Bad sub-register");
- Mov = AddDefaultPred(BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
- .addReg(Src));
+ Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
+ .addReg(Src);
// VORR takes two source operands.
if (Opc == ARM::VORRq)
Mov.addReg(Src);
+ Mov = AddDefaultPred(Mov);
}
// Add implicit super-register defs and kills to the last instruction.
Mov->addRegisterDefined(DestReg, TRI);
Added: llvm/trunk/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll?rev=162703&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2012-08-27-CopyPhysRegCrash.ll Mon Aug 27 17:12:44 2012
@@ -0,0 +1,129 @@
+; RUN: llc < %s -mcpu=cortex-a8 -march=thumb
+; Test that this doesn't crash.
+; <rdar://problem/12183003>
+
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
+target triple = "thumbv7-apple-ios5.1.0"
+
+declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8*, i32) nounwind readonly
+
+declare void @llvm.arm.neon.vst1.v16i8(i8*, <16 x i8>, i32) nounwind
+
+define void @findEdges(i8*) nounwind ssp {
+ %2 = icmp sgt i32 undef, 0
+ br i1 %2, label %5, label %3
+
+; <label>:3 ; preds = %5, %1
+ %4 = phi i8* [ %0, %1 ], [ %19, %5 ]
+ ret void
+
+; <label>:5 ; preds = %5, %1
+ %6 = phi i8* [ %19, %5 ], [ %0, %1 ]
+ %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* null, i32 1)
+ %8 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %7, 0
+ %9 = getelementptr inbounds i8* null, i32 3
+ %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %9, i32 1)
+ %11 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %10, 2
+ %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %6, i32 1)
+ %13 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 0
+ %14 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %12, 1
+ %15 = getelementptr inbounds i8* %6, i32 3
+ %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8(i8* %15, i32 1)
+ %17 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 1
+ %18 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %16, 2
+ %19 = getelementptr inbounds i8* %6, i32 48
+ %20 = bitcast <16 x i8> %13 to <2 x i64>
+ %21 = bitcast <16 x i8> %8 to <2 x i64>
+ %22 = bitcast <16 x i8> %14 to <2 x i64>
+ %23 = shufflevector <2 x i64> %22, <2 x i64> undef, <1 x i32> zeroinitializer
+ %24 = bitcast <1 x i64> %23 to <8 x i8>
+ %25 = zext <8 x i8> %24 to <8 x i16>
+ %26 = sub <8 x i16> zeroinitializer, %25
+ %27 = bitcast <16 x i8> %17 to <2 x i64>
+ %28 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %26) nounwind
+ %29 = mul <8 x i16> %28, %28
+ %30 = add <8 x i16> zeroinitializer, %29
+ %31 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> undef, <8 x i16> %30) nounwind
+ %32 = bitcast <16 x i8> %11 to <2 x i64>
+ %33 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> zeroinitializer
+ %34 = bitcast <1 x i64> %33 to <8 x i8>
+ %35 = zext <8 x i8> %34 to <8 x i16>
+ %36 = sub <8 x i16> %35, zeroinitializer
+ %37 = bitcast <16 x i8> %18 to <2 x i64>
+ %38 = shufflevector <2 x i64> %37, <2 x i64> undef, <1 x i32> zeroinitializer
+ %39 = bitcast <1 x i64> %38 to <8 x i8>
+ %40 = zext <8 x i8> %39 to <8 x i16>
+ %41 = sub <8 x i16> zeroinitializer, %40
+ %42 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %36) nounwind
+ %43 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %41) nounwind
+ %44 = mul <8 x i16> %42, %42
+ %45 = mul <8 x i16> %43, %43
+ %46 = add <8 x i16> %45, %44
+ %47 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %31, <8 x i16> %46) nounwind
+ %48 = bitcast <8 x i16> %47 to <2 x i64>
+ %49 = shufflevector <2 x i64> %48, <2 x i64> undef, <1 x i32> zeroinitializer
+ %50 = bitcast <1 x i64> %49 to <4 x i16>
+ %51 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %50, <4 x i16> undef) nounwind
+ %52 = tail call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %51, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
+ %53 = bitcast <4 x i16> %52 to <1 x i64>
+ %54 = shufflevector <1 x i64> %53, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
+ %55 = bitcast <2 x i64> %54 to <8 x i16>
+ %56 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %55, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
+ %57 = shufflevector <2 x i64> %20, <2 x i64> undef, <1 x i32> <i32 1>
+ %58 = bitcast <1 x i64> %57 to <8 x i8>
+ %59 = zext <8 x i8> %58 to <8 x i16>
+ %60 = sub <8 x i16> zeroinitializer, %59
+ %61 = shufflevector <2 x i64> %21, <2 x i64> undef, <1 x i32> <i32 1>
+ %62 = bitcast <1 x i64> %61 to <8 x i8>
+ %63 = zext <8 x i8> %62 to <8 x i16>
+ %64 = sub <8 x i16> %63, zeroinitializer
+ %65 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %60) nounwind
+ %66 = mul <8 x i16> %65, %65
+ %67 = add <8 x i16> zeroinitializer, %66
+ %68 = shufflevector <2 x i64> %27, <2 x i64> undef, <1 x i32> <i32 1>
+ %69 = bitcast <1 x i64> %68 to <8 x i8>
+ %70 = zext <8 x i8> %69 to <8 x i16>
+ %71 = sub <8 x i16> zeroinitializer, %70
+ %72 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> undef) nounwind
+ %73 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %71) nounwind
+ %74 = mul <8 x i16> %72, %72
+ %75 = mul <8 x i16> %73, %73
+ %76 = add <8 x i16> %75, %74
+ %77 = shufflevector <2 x i64> %32, <2 x i64> undef, <1 x i32> <i32 1>
+ %78 = bitcast <1 x i64> %77 to <8 x i8>
+ %79 = zext <8 x i8> %78 to <8 x i16>
+ %80 = sub <8 x i16> %79, zeroinitializer
+ %81 = tail call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %80) nounwind
+ %82 = mul <8 x i16> %81, %81
+ %83 = add <8 x i16> zeroinitializer, %82
+ %84 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %76, <8 x i16> %83) nounwind
+ %85 = tail call <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16> %67, <8 x i16> %84) nounwind
+ %86 = bitcast <8 x i16> %85 to <2 x i64>
+ %87 = shufflevector <2 x i64> %86, <2 x i64> undef, <1 x i32> <i32 1>
+ %88 = bitcast <1 x i64> %87 to <4 x i16>
+ %89 = tail call <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16> %88, <4 x i16> undef) nounwind
+ %90 = tail call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %89, <4 x i32> <i32 -6, i32 -6, i32 -6, i32 -6>)
+ %91 = bitcast <4 x i16> %90 to <1 x i64>
+ %92 = shufflevector <1 x i64> undef, <1 x i64> %91, <2 x i32> <i32 0, i32 1>
+ %93 = bitcast <2 x i64> %92 to <8 x i16>
+ %94 = tail call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %93, <8 x i16> <i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8>)
+ %95 = bitcast <8 x i8> %56 to <1 x i64>
+ %96 = bitcast <8 x i8> %94 to <1 x i64>
+ %97 = shufflevector <1 x i64> %95, <1 x i64> %96, <2 x i32> <i32 0, i32 1>
+ %98 = bitcast <2 x i64> %97 to <16 x i8>
+ tail call void @llvm.arm.neon.vst1.v16i8(i8* null, <16 x i8> %98, i32 1)
+ %99 = icmp slt i32 undef, undef
+ br i1 %99, label %5, label %3
+}
+
+declare <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
+
+declare <4 x i32> @llvm.arm.neon.vmullu.v4i32(<4 x i16>, <4 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vmaxu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
+
+declare <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16>) nounwind readnone
More information about the llvm-commits
mailing list