[llvm-commits] [RFC/PATCH] introduce 'UseSSEx' predicates

Michael Liao michael.liao at intel.com
Wed Aug 22 10:27:49 PDT 2012


The attached patch adds several new predicates, namely UseSSE1, UseSSE2,
UseSSE3, UseSSSE3, UseSSE41, and UseSSE42.

As the penalty of inter-mixing SSE and AVX instructions, we need prevent
SSE legacy insn from being generated except explicitly specified through
some intrinsics. For patterns both supported by both SSE and AVX, so
far, we force AVX insn will be tried first relying on AddedComplexity or
td location. It's error-prone and introduces bugs accidentally.

'UseSSEx' is disabled when AVX is turned on. For insns both supported by
AVX and SSE insns, we need this predicate to force VEX encoding only.

For insns not inherited by AVX, we still use the previous predicates,
i.e. 'HasSSEx'. So far, these insns fall into the following categories:
  * SSE insns with MMX operands
  * SSE insns with GPR/mem operands only (xFENCE, PREFETCH, CLFLUSH,
    CRC, and etc.)
  * SSE4A insns.
  * MMX insns.
  * x87 insns added by SSE.

With this patch, several inter-mixing cases are found and fixed from
regression tests.

Please review this patch.

- Michael

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