[llvm-commits] [llvm] r162192 - /llvm/trunk/lib/Target/X86/X86InstrFMA.td
Craig Topper
craig.topper at gmail.com
Sun Aug 19 16:37:46 PDT 2012
Author: ctopper
Date: Sun Aug 19 18:37:46 2012
New Revision: 162192
URL: http://llvm.org/viewvc/llvm-project?rev=162192&view=rev
Log:
Remove trailing white space and tab characters. No functional change.
Modified:
llvm/trunk/lib/Target/X86/X86InstrFMA.td
Modified: llvm/trunk/lib/Target/X86/X86InstrFMA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?rev=162192&r1=162191&r2=162192&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFMA.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFMA.td Sun Aug 19 18:37:46 2012
@@ -20,21 +20,21 @@
let neverHasSideEffects = 1 in {
def r : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
let mayLoad = 1 in
def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, VR256:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
let mayLoad = 1 in
def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
} // neverHasSideEffects = 1
}
@@ -42,8 +42,8 @@
// Intrinsic for 213 pattern
multiclass fma3p_rm_int<bits<8> opc, string OpcodeStr,
PatFrag MemFrag128, PatFrag MemFrag256,
- Intrinsic Int128, Intrinsic Int256, SDNode Op213,
- ValueType OpVT128, ValueType OpVT256> {
+ Intrinsic Int128, Intrinsic Int256, SDNode Op213,
+ ValueType OpVT128, ValueType OpVT256> {
def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
@@ -55,7 +55,7 @@
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
+ [(set VR128:$dst, (OpVT128 (Op213 VR128:$src2,
VR128:$src1, VR128:$src3)))]>;
def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
@@ -67,7 +67,7 @@
def m : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst, (OpVT128 (Op213 VR128:$src2, VR128:$src1,
(MemFrag128 addr:$src3))))]>;
@@ -75,31 +75,31 @@
def rY_Int : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, VR256:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
+ [(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
VR256:$src3))]>;
def rY : FMA3<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, VR256:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR256:$dst, (OpVT256 (Op213 VR256:$src2, VR256:$src1,
VR256:$src3)))]>;
def mY_Int : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
+ [(set VR256:$dst, (Int256 VR256:$src2, VR256:$src1,
(MemFrag256 addr:$src3)))]>;
def mY : FMA3<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, f256mem:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR256:$dst,
- (OpVT256 (Op213 VR256:$src2, VR256:$src1,
+ (OpVT256 (Op213 VR256:$src2, VR256:$src1,
(MemFrag256 addr:$src3))))]>;
}
} // Constraints = "$src1 = $dst"
@@ -112,9 +112,9 @@
defm r213 : fma3p_rm_int <opc213, !strconcat(OpcodeStr,
!strconcat("213", PackTy)), MemFrag128, MemFrag256,
Int128, Int256, Op, OpTy128, OpTy256>;
- defm r132 : fma3p_rm <opc132,
+ defm r132 : fma3p_rm <opc132,
!strconcat(OpcodeStr, !strconcat("132", PackTy))>;
- defm r231 : fma3p_rm <opc231,
+ defm r231 : fma3p_rm <opc231,
!strconcat(OpcodeStr, !strconcat("231", PackTy))>;
}
@@ -125,16 +125,16 @@
int_x86_fma_vfmadd_ps_256, X86Fmadd,
v4f32, v8f32>;
defm VFMSUBPS : fma3p_forms<0x9A, 0xAA, 0xBA, "vfmsub", "ps", memopv4f32,
- memopv8f32, int_x86_fma_vfmsub_ps,
+ memopv8f32, int_x86_fma_vfmsub_ps,
int_x86_fma_vfmsub_ps_256, X86Fmsub,
v4f32, v8f32>;
defm VFMADDSUBPS : fma3p_forms<0x96, 0xA6, 0xB6, "vfmaddsub", "ps",
- memopv4f32, memopv8f32,
+ memopv4f32, memopv8f32,
int_x86_fma_vfmaddsub_ps,
- int_x86_fma_vfmaddsub_ps_256, X86Fmaddsub,
+ int_x86_fma_vfmaddsub_ps_256, X86Fmaddsub,
v4f32, v8f32>;
defm VFMSUBADDPS : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "ps",
- memopv4f32, memopv8f32,
+ memopv4f32, memopv8f32,
int_x86_fma_vfmsubadd_ps,
int_x86_fma_vfmaddsub_ps_256, X86Fmsubadd,
v4f32, v8f32>;
@@ -155,7 +155,7 @@
int_x86_fma_vfmaddsub_pd_256, X86Fmaddsub,
v2f64, v4f64>, VEX_W;
defm VFMSUBADDPD : fma3p_forms<0x97, 0xA7, 0xB7, "vfmsubadd", "pd",
- memopv2f64, memopv4f64,
+ memopv2f64, memopv4f64,
int_x86_fma_vfmsubadd_pd,
int_x86_fma_vfmsubadd_pd_256, X86Fmsubadd,
v2f64, v4f64>, VEX_W;
@@ -190,47 +190,47 @@
let neverHasSideEffects = 1 in {
def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
let mayLoad = 1 in
def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, RC:$src2, x86memop:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
} // neverHasSideEffects = 1
}
multiclass fma3s_rm_int<bits<8> opc, string OpcodeStr, Operand memop,
- ComplexPattern mem_cpat, Intrinsic IntId,
+ ComplexPattern mem_cpat, Intrinsic IntId,
RegisterClass RC, SDNode OpNode, ValueType OpVT> {
def r_Int : FMA3<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
- !strconcat(OpcodeStr,
- "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
- [(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
+ !strconcat(OpcodeStr,
+ "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
+ [(set VR128:$dst, (IntId VR128:$src2, VR128:$src1,
VR128:$src3))]>;
def m_Int : FMA3<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, memop:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set VR128:$dst,
(IntId VR128:$src2, VR128:$src1, mem_cpat:$src3))]>;
def r : FMA3<opc, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, RC:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[(set RC:$dst,
- (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
+ (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
let mayLoad = 1 in
def m : FMA3<opc, MRMSrcMem, (outs RC:$dst),
(ins RC:$src1, RC:$src2, memop:$src3),
- !strconcat(OpcodeStr,
+ !strconcat(OpcodeStr,
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"), []>;
}
} // Constraints = "$src1 = $dst"
multiclass fma3s_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
- string OpStr, Intrinsic IntF32, Intrinsic IntF64,
+ string OpStr, Intrinsic IntF32, Intrinsic IntF64,
SDNode OpNode> {
defm SSr132 : fma3s_rm<opc132, !strconcat(OpStr, "132ss"), f32mem, FR32>;
defm SSr231 : fma3s_rm<opc231, !strconcat(OpStr, "231ss"), f32mem, FR32>;
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