[llvm-commits] [PATCH][Please review] Enable Vector Select for ARM

[Stephen Hines]

I think Arnold intended for the test case to be added to the changelist.
Such a test would go into the test/CodeGen/ARM subdirectory and follow the
standard practices (i.e. CHECK annotations for the expected output, etc.).

Steve


On Tue, Aug 14, 2012 at 3:55 PM, Yin Ma <yinma at codeaurora.org> wrote:

> Hi Arnold,
>
>     Here we go. This is the test case.
>
>               Yin
>
> -----Original Message-----
> From: Arnold Schwaighofer [mailto:arnolds at codeaurora.org]
> Sent: Tuesday, August 14, 2012 2:17 PM
> To: Yin Ma
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [PATCH][Please review] Enable Vector Select for
> ARM
>
> Can you add a test case?
>
> -    // Since only 64-bit and 128-bit vectors are legal on ARM and
> -    // we've eliminated the other cases...
> -    assert(SourceVecs[i].getValueType().getVectorNumElements() ==
> 2*NumElts &&
> -           "unexpected vector sizes in ReconstructShuffle");
>
> The comments above the removed assert look suspicious. They seem to
> indicate
> that this case was supposed to be handle further up/else where?
>
> Best,
> Arnold
>
> On 8/14/2012 1:52 PM, Yin Ma wrote:
> > Hi,
> >
> > So far vector select, such as  a < b ? a : c, when IR is generated for
> > vector
> >
> > select on ARM. The ARM backend will trigger an assertion. The patch
> > will
> >
> > add a handler code to make assertion go away.
> >
> >     Please give a review again.
> >
> > Thanks,
> >
> >                 Yin
> >
> >
> >
> > _______________________________________________
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> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> >
>
>
>
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