[llvm-commits] [PATCH][Please review] Enable Vector Select for ARM

[Arnold Schwaighofer]

Can you add a test case?

-    // Since only 64-bit and 128-bit vectors are legal on ARM and
-    // we've eliminated the other cases...
-    assert(SourceVecs[i].getValueType().getVectorNumElements() == 
2*NumElts &&
-           "unexpected vector sizes in ReconstructShuffle");

The comments above the removed assert look suspicious. They seem to 
indicate that this case was supposed to be handle further up/else where?

Best,
Arnold

On 8/14/2012 1:52 PM, Yin Ma wrote:
> Hi,
>
> So far vector select, such as  a < b ? a : c, when IR is generated for
> vector
>
> select on ARM. The ARM backend will trigger an assertion. The patch will
>
> add a handler code to make assertion go away.
>
>     Please give a review again.
>
> Thanks,
>
>                 Yin
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>



-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.