[llvm-commits] [llvm] r161728 - in /llvm/trunk: lib/CodeGen/MachineCSE.cpp test/CodeGen/X86/lsr-loop-exit-cond.ll test/CodeGen/X86/machine-cse.ll

[Benjamin Kramer]

Author: d0k
Date: Sat Aug 11 14:05:13 2012
New Revision: 161728

URL: http://llvm.org/viewvc/llvm-project?rev=161728&view=rev
Log:
PR13578: Teach MachineCSE that instructions that use a constant register can be CSE'd safely.

This is common e.g. when doing rip-relative addressing on x86_64.

Modified:
    llvm/trunk/lib/CodeGen/MachineCSE.cpp
    llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll
    llvm/trunk/test/CodeGen/X86/machine-cse.ll

Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=161728&r1=161727&r2=161728&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Sat Aug 11 14:05:13 2012
@@ -215,8 +215,11 @@
     if (MO.isDef() &&
         (MO.isDead() || isPhysDefTriviallyDead(Reg, I, MBB->end())))
       continue;
-    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
-      PhysRefs.insert(*AI);
+    for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
+      // Reading constant physregs is ok.
+      if (!MRI->isConstantPhysReg(*AI, *MBB->getParent()))
+        PhysRefs.insert(*AI);
+    }
     if (MO.isDef())
       PhysDefs.push_back(Reg);
   }

Modified: llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll?rev=161728&r1=161727&r2=161728&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-loop-exit-cond.ll Sat Aug 11 14:05:13 2012
@@ -3,11 +3,11 @@
 
 ; CHECK: t:
 ; CHECK: decq
-; CHECK-NEXT: movl (%r11,%rax,4), %eax
+; CHECK-NEXT: movl (%r9,%rax,4), %eax
 ; CHECK-NEXT: jne
 
 ; ATOM: t:
-; ATOM: movl (%r10,%rax,4), %eax
+; ATOM: movl (%r9,%rax,4), %eax
 ; ATOM-NEXT: decq
 ; ATOM-NEXT: jne
 

Modified: llvm/trunk/test/CodeGen/X86/machine-cse.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/machine-cse.ll?rev=161728&r1=161727&r2=161728&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/machine-cse.ll (original)
+++ llvm/trunk/test/CodeGen/X86/machine-cse.ll Sat Aug 11 14:05:13 2012
@@ -134,3 +134,25 @@
   %retval.0 = phi i8* [ null, %entry ], [ null, %do.cond ], [ %p.0, %do.body ]
   ret i8* %retval.0
 }
+
+; PR13578
+ at t2_global = external global i32
+
+declare i1 @t2_func()
+
+define i32 @t2() {
+  store i32 42, i32* @t2_global
+  %c = call i1 @t2_func()
+  br i1 %c, label %a, label %b
+
+a:
+  %l = load i32* @t2_global
+  ret i32 %l
+
+b:
+  ret i32 0
+
+; CHECK: t2:
+; CHECK: t2_global at GOTPCREL(%rip)
+; CHECK-NOT: t2_global at GOTPCREL(%rip)
+}