[llvm-commits] [llvm] r161302 - in /llvm/trunk: include/llvm/Target/TargetSelectionDAG.td lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCInstr64Bit.td test/CodeGen/PowerPC/ppc64-cyclecounter.ll
Hal Finkel
hfinkel at anl.gov
Sat Aug 4 07:10:46 PDT 2012
Author: hfinkel
Date: Sat Aug 4 09:10:46 2012
New Revision: 161302
URL: http://llvm.org/viewvc/llvm-project?rev=161302&view=rev
Log:
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
Added:
llvm/trunk/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
Modified:
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=161302&r1=161301&r2=161302&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Sat Aug 4 09:10:46 2012
@@ -411,6 +411,9 @@
[SDNPHasChain, SDNPMayLoad, SDNPMayStore,
SDNPMemOperand]>;
+def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
+ [SDNPHasChain, SDNPSideEffect]>;
+
def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
[SDNPHasChain, SDNPSideEffect]>;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=161302&r1=161301&r2=161302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Sat Aug 4 09:10:46 2012
@@ -394,8 +394,10 @@
setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
}
- if (Subtarget->has64BitSupport())
+ if (Subtarget->has64BitSupport()) {
setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
+ setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
+ }
setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=161302&r1=161301&r2=161302&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Sat Aug 4 09:10:46 2012
@@ -265,6 +265,11 @@
PPC970_DGroup_First, PPC970_Unit_FXU;
}
+let Pattern = [(set G8RC:$rT, readcyclecounter)] in
+def MFTB8 : XFXForm_1_ext<31, 371, 268, (outs G8RC:$rT), (ins),
+ "mftb $rT", SprMFTB>,
+ PPC970_DGroup_First, PPC970_Unit_FXU;
+
let Defs = [X1], Uses = [X1] in
def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
[(set G8RC:$result,
Added: llvm/trunk/test/CodeGen/PowerPC/ppc64-cyclecounter.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-cyclecounter.ll?rev=161302&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-cyclecounter.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-cyclecounter.ll Sat Aug 4 09:10:46 2012
@@ -0,0 +1,15 @@
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+; RUN: llc < %s | FileCheck %s
+
+define i64 @test1() nounwind {
+entry:
+ %r = call i64 @llvm.readcyclecounter()
+ ret i64 %r
+}
+
+; CHECK: @test1
+; CHECK: mftb
+
+declare i64 @llvm.readcyclecounter()
+
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