[llvm-commits] Add support for shl, lshr, and ashr instructions

[Chad Rosier]

Jush,
In the case that the shift amount is zero or greater then the width of the value type, should we just fall back to selection DAG isel to ensure we have consistent behavior (in the event that selection DAG isel changes)?  Perhaps someone else could comment on this.

My only other suggestion would be to simplify the test cases.  For example,

define i32 @shl() nounwind ssp {
entry:
  %shl = shl i32 -1, 2
  ret i32 %shl
}

define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp {
entry:
  %shl = shl i32 %src1, %src2
  ret i32 %shl
}

define i32 @lshr() nounwind ssp {
entry:
  %lshr = lshr i32 -1, 2
  ret i32 %lshr
}

define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp {
entry:
  %lshr = lshr i32 %src1, %src2
  ret i32 %lshr
}

define i32 @ashr() nounwind ssp {
entry:
  %ashr = ashr i32 -1, 2
  ret i32 %ashr
}

define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp {
entry:
  %ashr = ashr i32 %src1, %src2
  ret i32 %ashr
}

Basically, I ran mem2reg on your test cases… :)  

While I realize this isn't the type of code fast-isel is going to generate, this is much more concise in terms of what you're trying to test (and that's all we care about).

Please apply after updating the test cases.  If anyone disagrees with the handing of the zero/32 shift we can handle that as a post commit; I'm ok with leaving as is..

 Chad


On Jul 31, 2012, at 11:05 PM, Jush Lu wrote:

> Hi
> 
> This patch makes ARMFastISel able to handle shl, lshr, and ashr instructions, please help me review it, thanks.
> 
> Jush <fast-isel-shifter.patch>

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