[llvm-commits] [PATCH] revise/enhance atomic primitive code generation

[Michael Liao]

On Wed, 2012-07-25 at 15:34 -0700, Chandler Carruth wrote:
> First off, these sound like fantastic enhancements! =] Thanks for
> pulling them out.
> 
> 
> Can you split this into separate patches and post them individually
> for review? I think each of your bullet points would make for a good
> patch to review.

Definitely, I will re-submit them late today or early tomorrow.

Thanks
- Michael

> 
> 
> On Wed, Jul 25, 2012 at 3:06 PM, Michael Liao <michael.liao at intel.com>
> wrote:
>         - unify the logic in SelectAtomicLoadAdd and
>         SelectAtomicLoadArith and
>           merge them together
>         - refine spin-loop to reduce one unnecessary load
>         - add missing i8 max/min/umax/umin
>         - add missing i64 max/min/umax/umin on 32-bit target
>         - refine atomic instruction td files to use the template for
>         groups of
>           instructions
>         - Output 'lock' prefix in assembler printer to simplify the
>         assembly
>           text in td files
>         
>         Please review the attached patch and commit if it's OK.
>         
>         Yours
>         - Michael
>         
>         ---
>         [1] http://software.intel.com/file/36945
>         [2]
>         http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/
>         
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>