[llvm-commits] [llvm] r160703 - in /llvm/trunk: lib/Target/Mips/MipsFrameLowering.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsMachineFunction.h lib/Target/Mips/MipsRegisterInfo.cpp test/CodeGen/Mips/i64arg.ll test/CodeGen/Mips/largeimmprinting.ll test/CodeGen/Mips/o32_cc_byval.ll test/CodeGen/Mips/o32_cc_vararg.ll
Akira Hatanaka
ahatanaka at mips.com
Tue Jul 24 20:16:47 PDT 2012
Author: ahatanak
Date: Tue Jul 24 22:16:47 2012
New Revision: 160703
URL: http://llvm.org/viewvc/llvm-project?rev=160703&view=rev
Log:
Eliminate the stack slot used to save the global base register.
The long branch pass (fixed in r160601) no longer uses the global base register
to compute addresses of branch destinations, so it is not necessary to reserve
a slot on the stack.
Modified:
llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
llvm/trunk/test/CodeGen/Mips/i64arg.ll
llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Tue Jul 24 22:16:47 2012
@@ -113,11 +113,7 @@
// First, compute final stack size.
unsigned StackAlign = getStackAlignment();
uint64_t StackSize = RoundUpToAlignment(MFI->getStackSize(), StackAlign);
-
- if (MipsFI->globalBaseRegSet())
- StackSize += MFI->getObjectOffset(MipsFI->getGlobalRegFI()) + StackAlign;
- else
- StackSize += RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign);
+ StackSize += RoundUpToAlignment(MipsFI->getMaxCallFrameSize(), StackAlign);
// Update stack size
MFI->setStackSize(StackSize);
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Tue Jul 24 22:16:47 2012
@@ -117,28 +117,23 @@
void MipsDAGToDAGISel::InitGlobalBaseReg(MachineFunction &MF) {
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
- if (((MF.getTarget().getRelocationModel() == Reloc::Static) ||
- Subtarget.inMips16Mode()) && !MipsFI->globalBaseRegSet())
+ if (!MipsFI->globalBaseRegSet())
return;
MachineBasicBlock &MBB = MF.front();
MachineBasicBlock::iterator I = MBB.begin();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
- const MipsRegisterInfo *TargetRegInfo = TM.getRegisterInfo();
- const MipsInstrInfo *MII = TM.getInstrInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg();
- int FI = 0;
+ const TargetRegisterClass *RC;
- FI= MipsFI->initGlobalRegFI();
-
- const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
- (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
- (const TargetRegisterClass*)&Mips::CPURegsRegClass;
-
- if (Subtarget.inMips16Mode())
- RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
+ if (Subtarget.isABI_N64())
+ RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
+ else if (Subtarget.inMips16Mode())
+ RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
+ else
+ RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
V0 = RegInfo.createVirtualRegister(RC);
V1 = RegInfo.createVirtualRegister(RC);
@@ -158,23 +153,17 @@
.addReg(Mips::T9_64);
BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
- MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
- TargetRegInfo);
return;
}
if (Subtarget.inMips16Mode()) {
BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
- .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
- BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16),
- V1)
- .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
- BuildMI(MBB, I, DL, TII.get(Mips::SllX16),
- V2 ).addReg(V0).addImm(16);
+ .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
+ BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
+ .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
+ BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
.addReg(V1).addReg(V2);
-
-
return;
}
@@ -203,19 +192,11 @@
BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
- MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC,
- TargetRegInfo);
return;
}
assert(Subtarget.isABI_O32());
-
- //if (Subtarget.inMips16Mode())
- // return; // no need to load GP. It can be calculated anywhere
-
-
-
// For O32 ABI, the following instruction sequence is emitted to initialize
// the global base register:
//
@@ -237,7 +218,6 @@
MBB.addLiveIn(Mips::V0);
BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
.addReg(Mips::V0).addReg(Mips::T9);
- MII->storeRegToStackSlot(MBB, I, GlobalBaseReg, false, FI, RC, TargetRegInfo);
}
bool MipsDAGToDAGISel::ReplaceUsesWithZeroReg(MachineRegisterInfo *MRI,
Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Tue Jul 24 22:16:47 2012
@@ -48,7 +48,6 @@
// OutArgFIRange: Range of indices of all frame objects created during call to
// LowerCall except for the frame object for restoring $gp.
std::pair<int, int> InArgFIRange, OutArgFIRange;
- int GlobalRegFI;
mutable int DynAllocFI; // Frame index of dynamically allocated stack area.
unsigned MaxCallFrameSize;
@@ -58,7 +57,7 @@
MipsFunctionInfo(MachineFunction& MF)
: MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
- OutArgFIRange(std::make_pair(-1, 0)), GlobalRegFI(0), DynAllocFI(0),
+ OutArgFIRange(std::make_pair(-1, 0)), DynAllocFI(0),
MaxCallFrameSize(0), EmitNOAT(false)
{}
@@ -77,24 +76,6 @@
OutArgFIRange.second = LastFI;
}
- bool isGlobalRegFI(int FI) const {
- return GlobalRegFI && (FI == GlobalRegFI);
- }
-
- int getGlobalRegFI() const {
- return GlobalRegFI;
- }
-
- int initGlobalRegFI() {
- const TargetMachine &TM = MF.getTarget();
- unsigned RegSize = TM.getSubtarget<MipsSubtarget>().isABI_N64() ? 8 : 4;
- int64_t StackAlignment = TM.getFrameLowering()->getStackAlignment();
- uint64_t Offset = RoundUpToAlignment(MaxCallFrameSize, StackAlignment);
-
- GlobalRegFI = MF.getFrameInfo()->CreateFixedObject(RegSize, Offset, true);
- return GlobalRegFI;
- }
-
// The first call to this function creates a frame object for dynamically
// allocated stack area.
int getDynAllocFI() const {
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Jul 24 22:16:47 2012
@@ -214,8 +214,7 @@
// incoming argument, callee-saved register location or local variable.
int64_t Offset;
- if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
- MipsFI->isGlobalRegFI(FrameIndex))
+ if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex))
Offset = spOffset;
else
Offset = spOffset + (int64_t)stackSize;
Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Tue Jul 24 22:16:47 2012
@@ -10,8 +10,8 @@
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 88($sp)
-; CHECK: lw $[[R3:[0-9]+]], 92($sp)
+; CHECK: lw $[[R2:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Tue Jul 24 22:16:47 2012
@@ -7,7 +7,7 @@
define void @f() nounwind {
entry:
; CHECK: lui $at, 65534
-; CHECK: addiu $at, $at, -24
+; CHECK: addiu $at, $at, -16
; CHECK: addu $sp, $sp, $at
%agg.tmp = alloca %struct.S1, align 1
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Tue Jul 24 22:16:47 2012
@@ -43,16 +43,16 @@
define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: lw $4, 88($sp)
-; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 72($sp)
-; CHECK: lw $[[R4:[0-9]+]], 76($sp)
-; CHECK: lw $[[R2:[0-9]+]], 68($sp)
-; CHECK: lh $[[R1:[0-9]+]], 66($sp)
-; CHECK: lb $[[R0:[0-9]+]], 64($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: lw $4, 80($sp)
+; CHECK: ldc1 $f[[F0:[0-9]+]], 72($sp)
+; CHECK: lw $[[R3:[0-9]+]], 64($sp)
+; CHECK: lw $[[R4:[0-9]+]], 68($sp)
+; CHECK: lw $[[R2:[0-9]+]], 60($sp)
+; CHECK: lh $[[R1:[0-9]+]], 58($sp)
+; CHECK: lb $[[R0:[0-9]+]], 56($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R2]], 24($sp)
@@ -80,13 +80,13 @@
define void @f3(%struct.S2* nocapture byval %s2) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: sw $5, 60($sp)
-; CHECK: sw $4, 56($sp)
-; CHECK: lw $4, 56($sp)
-; CHECK: lw $[[R0:[0-9]+]], 68($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: sw $4, 48($sp)
+; CHECK: lw $4, 48($sp)
+; CHECK: lw $[[R0:[0-9]+]], 60($sp)
; CHECK: sw $[[R0]], 24($sp)
%arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0
@@ -99,13 +99,13 @@
define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
entry:
-; CHECK: addiu $sp, $sp, -56
-; CHECK: sw $7, 68($sp)
-; CHECK: sw $6, 64($sp)
-; CHECK: sw $5, 60($sp)
-; CHECK: lw $4, 68($sp)
-; CHECK: lw $[[R1:[0-9]+]], 88($sp)
-; CHECK: lb $[[R0:[0-9]+]], 60($sp)
+; CHECK: addiu $sp, $sp, -48
+; CHECK: sw $7, 60($sp)
+; CHECK: sw $6, 56($sp)
+; CHECK: sw $5, 52($sp)
+; CHECK: lw $4, 60($sp)
+; CHECK: lw $[[R1:[0-9]+]], 80($sp)
+; CHECK: lb $[[R0:[0-9]+]], 52($sp)
; CHECK: sw $[[R0]], 32($sp)
; CHECK: sw $[[R1]], 24($sp)
Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=160703&r1=160702&r2=160703&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Tue Jul 24 22:16:47 2012
@@ -29,11 +29,11 @@
ret i32 %tmp
; CHECK: va1:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: sw $6, 32($sp)
-; CHECK: sw $5, 28($sp)
-; CHECK: lw $2, 28($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: lw $2, 20($sp)
}
; check whether the variable double argument will be accessed from the 8-byte
@@ -55,11 +55,11 @@
ret double %tmp
; CHECK: va2:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: sw $6, 32($sp)
-; CHECK: sw $5, 28($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 28
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: sw $5, 20($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 20
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -83,10 +83,10 @@
ret i32 %tmp
; CHECK: va3:
-; CHECK: addiu $sp, $sp, -24
-; CHECK: sw $7, 36($sp)
-; CHECK: sw $6, 32($sp)
-; CHECK: lw $2, 32($sp)
+; CHECK: addiu $sp, $sp, -16
+; CHECK: sw $7, 28($sp)
+; CHECK: sw $6, 24($sp)
+; CHECK: lw $2, 24($sp)
}
; double
@@ -106,11 +106,11 @@
ret double %tmp
; CHECK: va4:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: sw $7, 44($sp)
-; CHECK: sw $6, 40($sp)
-; CHECK: addiu ${{[0-9]+}}, $sp, 40
-; CHECK: ldc1 $f0, 40($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: sw $6, 32($sp)
+; CHECK: addiu ${{[0-9]+}}, $sp, 32
+; CHECK: ldc1 $f0, 32($sp)
}
; int
@@ -134,9 +134,9 @@
ret i32 %tmp
; CHECK: va5:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: sw $7, 44($sp)
-; CHECK: lw $2, 44($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: lw $2, 36($sp)
}
; double
@@ -160,9 +160,9 @@
ret double %tmp
; CHECK: va6:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: sw $7, 44($sp)
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 44
+; CHECK: addiu $sp, $sp, -24
+; CHECK: sw $7, 36($sp)
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
@@ -188,8 +188,8 @@
ret i32 %tmp
; CHECK: va7:
-; CHECK: addiu $sp, $sp, -32
-; CHECK: lw $2, 48($sp)
+; CHECK: addiu $sp, $sp, -24
+; CHECK: lw $2, 40($sp)
}
; double
@@ -211,9 +211,9 @@
ret double %tmp
; CHECK: va8:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu ${{[0-9]+}}, $sp, 56
-; CHECK: ldc1 $f0, 56($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu ${{[0-9]+}}, $sp, 48
+; CHECK: ldc1 $f0, 48($sp)
}
; int
@@ -237,8 +237,8 @@
ret i32 %tmp
; CHECK: va9:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: lw $2, 60($sp)
+; CHECK: addiu $sp, $sp, -32
+; CHECK: lw $2, 52($sp)
}
; double
@@ -262,8 +262,8 @@
ret double %tmp
; CHECK: va10:
-; CHECK: addiu $sp, $sp, -40
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 60
+; CHECK: addiu $sp, $sp, -32
+; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; CHECK: addiu $[[R2:[0-9]+]], $zero, -8
; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]]
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