[llvm-commits] Please review: FMA implementation for X86 architecture

[Lang Hames]

Hi Elena,

The second DAG combine looks a bit off:

+    // fold (fsub x, -(fmul, y, z)) -> (fma (fneg y), z, x)

That implies:

x - -(y * z) ==> -y * z + a

Which isn't a valid transformation. You probably don't want the negate on
'y'.

+    if (N1.getOpcode() == ISD::FNEG &&
+        N1.getOperand(0).getOpcode() == ISD::FMUL &&
+        N1->hasOneUse() && N1.getOperand(0).hasOneUse()) {
+      SDValue N10 = N1.getOperand(0).getOperand(0);
+      SDValue N11 = N1.getOperand(0).getOperand(1);
+      return DAG.getNode(ISD::FMA, dl, VT,
+                         DAG.getNode(ISD::FNEG, N1->getDebugLoc(), VT,
N10),
+                         N11, N1);

Given the observation above, I think the ISD::FNEG should go away here.
Also N1 is being used as the RHS addend. I think that should be N0?

Otherwise it looks good to me.

Cheers,
Lang.


On Mon, Jul 23, 2012 at 8:43 AM, Demikhovsky, Elena <
elena.demikhovsky at intel.com> wrote:

>
> I added code generation for FMA patterns on AVX2 architecture.
>
> - Elena
>
>
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