[llvm-commits] [llvm] r160387 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/X86/X86ISelLowering.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll
Evan Cheng
evan.cheng at apple.com
Tue Jul 17 11:54:11 PDT 2012
Author: evancheng
Date: Tue Jul 17 13:54:11 2012
New Revision: 160387
URL: http://llvm.org/viewvc/llvm-project?rev=160387&view=rev
Log:
Back out r160101 and instead implement a dag combine to recover from instcombine transformation.
Removed:
llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=160387&r1=160386&r2=160387&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jul 17 13:54:11 2012
@@ -2716,6 +2716,34 @@
}
}
+ if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
+ VT.getSizeInBits() <= 64) {
+ if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+ APInt ADDC = ADDI->getAPIntValue();
+ if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
+ // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
+ // immediate for an add, but it is legal if its top c2 bits are set,
+ // transform the ADD so the immediate doesn't need to be materialized
+ // in a register.
+ if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+ APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
+ SRLI->getZExtValue());
+ if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
+ ADDC |= Mask;
+ if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
+ SDValue NewAdd =
+ DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT,
+ N0.getOperand(0), DAG.getConstant(ADDC, VT));
+ CombineTo(N0.getNode(), NewAdd);
+ return SDValue(N, 0); // Return N so it doesn't get rechecked!
+ }
+ }
+ }
+ }
+ }
+ }
+
+
return SDValue();
}
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=160387&r1=160386&r2=160387&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 17 13:54:11 2012
@@ -11345,6 +11345,7 @@
}
bool X86TargetLowering::isLegalAddImmediate(int64_t Imm) const {
+ // Can also use sub to handle negated immediates.
return Imm == (int32_t)Imm;
}
Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=160387&r1=160386&r2=160387&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Tue Jul 17 13:54:11 2012
@@ -40,13 +40,6 @@
// This instruction is producing bits that are not demanded. Shrink the RHS.
Demanded &= OpC->getValue();
- if (I->getOpcode() == Instruction::Add) {
- // However, if the instruction is an add then the constant may be negated
- // when the opcode is changed to sub. Check if the transformation is really
- // shrinking the constant.
- if (Demanded.abs().getActiveBits() > OpC->getValue().abs().getActiveBits())
- return false;
- }
I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
return true;
}
Removed: llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll?rev=160386&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: opt < %s -instcombine -S | FileCheck %s
-
-; When shrinking demanded constant operand of an add instruction, keep in
-; mind the opcode can be changed to sub and the constant negated. Make sure
-; the shrinking the constant would actually reduce the width.
-; rdar://11793464
-
-define i64 @t(i64 %key, i64* %val) nounwind {
-entry:
-; CHECK: @t
-; CHECK-NOT: add i64 %0, 2305843009213693951
-; CHECK: add i64 %0, -1
- %shr = lshr i64 %key, 3
- %0 = load i64* %val, align 8
- %sub = sub i64 %0, 1
- %and = and i64 %sub, %shr
- ret i64 %and
-}
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