[llvm-commits] [llvm] r160354 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp test/CodeGen/CellSPU/icmp32.ll test/CodeGen/X86/cmp.ll

[Eli Friedman]

On Tue, Jul 17, 2012 at 1:31 AM, Evan Cheng <evan.cheng at apple.com> wrote:
> Author: evancheng
> Date: Tue Jul 17 03:31:11 2012
> New Revision: 160354
>
> URL: http://llvm.org/viewvc/llvm-project?rev=160354&view=rev
> Log:
> Implement r160312 as target indepedenet dag combine.
>
> Modified:
>     llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
>     llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>     llvm/trunk/test/CodeGen/CellSPU/icmp32.ll
>     llvm/trunk/test/CodeGen/X86/cmp.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=160354&r1=160353&r2=160354&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Jul 17 03:31:11 2012
> @@ -2342,6 +2342,33 @@
>              return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
>            }
>          }
> +      } else if (Cond == ISD::SETULT || Cond == ISD::SETUGE ||
> +                 Cond == ISD::SETULE || Cond == ISD::SETUGT) {
> +        bool AdjOne = (Cond == ISD::SETULE || Cond == ISD::SETUGT);
> +        // X <  0x100000000 -> (X >> 32) <  1
> +        // X >= 0x100000000 -> (X >> 32) >= 1
> +        // X <= 0x0ffffffff -> (X >> 32) <  1
> +        // X >  0x0ffffffff -> (X >> 32) >= 1
> +        unsigned ShiftBits;
> +        APInt NewC = C1;
> +        ISD::CondCode NewCond = Cond;
> +        if (AdjOne) {
> +          ShiftBits = C1.countTrailingOnes();
> +          NewC = NewC + 1;
> +          NewCond = (Cond == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
> +        } else {
> +          ShiftBits = C1.countTrailingZeros();
> +        }
> +        NewC = NewC.lshr(ShiftBits);
> +        if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) {
> +          EVT ShiftTy = DCI.isBeforeLegalize() ?
> +            getPointerTy() : getShiftAmountTy(N0.getValueType());
> +          EVT CmpTy = N0.getValueType();
> +          SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0,
> +                                      DAG.getConstant(ShiftBits, ShiftTy));
> +          SDValue CmpRHS = DAG.getConstant(NewC, CmpTy);
> +          return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
> +        }
>        }
>      }
>    }
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=160354&r1=160353&r2=160354&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jul 17 03:31:11 2012
> @@ -3059,50 +3059,6 @@
>          RHS = DAG.getConstant(0, RHS.getValueType());
>          return X86::COND_LE;
>        }
> -      if (SetCCOpcode == ISD::SETULT || SetCCOpcode == ISD::SETUGE) {
> -        unsigned TrailZeros = RHSC->getAPIntValue().countTrailingZeros();
> -        if (TrailZeros >= 32) {
> -          // The constant doesn't fit in cmp immediate field. Right shift LHS by
> -          // the # of trailing zeros and truncate it to 32-bit. Then compare
> -          // against shifted RHS.
> -          assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
> -          DebugLoc dl = LHS.getDebugLoc();
> -          LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
> -                            DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
> -                                        DAG.getConstant(TrailZeros, MVT::i8)));
> -          uint64_t C = RHSC->getZExtValue() >> TrailZeros;
> -
> -          if (SetCCOpcode == ISD::SETULT) {
> -            // X < 0x300000000 -> (X >> 32) < 3
> -            // X < 0x100000000 -> (X >> 32) == 0
> -            // X < 0x200000000 -> (X >> 33) == 0
> -            if (C == 1) {
> -              RHS = DAG.getConstant(0, MVT::i32);
> -              return X86::COND_E;
> -            }
> -            RHS = DAG.getConstant(C, MVT::i32);
> -            return X86::COND_B;
> -          } else /* SetCCOpcode == ISD::SETUGE */ {
> -            // X >= 0x100000000 -> (X >> 32) >= 1
> -            RHS = DAG.getConstant(C, MVT::i32);
> -            return X86::COND_AE;
> -          }
> -        }
> -      }
> -      if (SetCCOpcode == ISD::SETUGT) {
> -        unsigned TrailOnes = RHSC->getAPIntValue().countTrailingOnes();
> -        if (TrailOnes >= 32 && !RHSC->isAllOnesValue()) {
> -          assert(LHS.getValueType() == MVT::i64 && "Expecting a 64-bit cmp!");
> -          DebugLoc dl = LHS.getDebugLoc();
> -          LHS = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,
> -                            DAG.getNode(ISD::SRL, dl, MVT::i64, LHS,
> -                                        DAG.getConstant(TrailOnes, MVT::i8)));
> -          uint64_t C = (RHSC->getZExtValue()+1) >> TrailOnes;
> -          // X >  0x0ffffffff -> (X >> 32) >= 1
> -          RHS = DAG.getConstant(C, MVT::i32);
> -          return X86::COND_AE;
> -        }
> -      }
>      }
>
>      switch (SetCCOpcode) {
>
> Modified: llvm/trunk/test/CodeGen/CellSPU/icmp32.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/icmp32.ll?rev=160354&r1=160353&r2=160354&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/CellSPU/icmp32.ll (original)
> +++ llvm/trunk/test/CodeGen/CellSPU/icmp32.ll Tue Jul 17 03:31:11 2012
> @@ -322,10 +322,8 @@
>
>  define i32 @icmp_ult_immed04_i32(i32 %arg1, i32 %val1, i32 %val2) nounwind {
>  ; CHECK:      icmp_ult_immed04_i32:
> -; CHECK:        ila
> -; CHECK:        ceq
> -; CHECK:        clgt
> -; CHECK:        nor
> +; CHECK:        rotmi
> +; CHECK:        ceqi
>  ; CHECK:        selb $3, $5, $4, $3
>
>  entry:
>
> Modified: llvm/trunk/test/CodeGen/X86/cmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmp.ll?rev=160354&r1=160353&r2=160354&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/cmp.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/cmp.ll Tue Jul 17 03:31:11 2012
> @@ -96,7 +96,7 @@
>  ; CHECK: test7:
>  ; CHECK-NOT: movabsq
>  ; CHECK: shrq $32, %rdi
> -; CHECK: testl %edi, %edi
> +; CHECK: testq %rdi, %rdi

Is there a bug filed on the missed optimization here?

-Eli