[llvm-commits] [llvm] r160221 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/2012-07-10-shufnorm.ll

[Nadav Rotem]

Author: nadav
Date: Sat Jul 14 16:30:27 2012
New Revision: 160221

URL: http://llvm.org/viewvc/llvm-project?rev=160221&view=rev
Log:
Add a dagcombine optimization to convert concat_vectors of undefs into a single undef.
The unoptimized concat_vectors isd prevented the canonicalization of the vector_shuffle node.


Added:
    llvm/trunk/test/CodeGen/X86/2012-07-10-shufnorm.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=160221&r1=160220&r2=160221&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jul 14 16:30:27 2012
@@ -7816,6 +7816,17 @@
   if (N->getNumOperands() == 1)
     return N->getOperand(0);
 
+  // Check if all of the operands are undefs.
+  bool AllUndef = true;
+  for (unsigned i = 0; i < N->getNumOperands(); ++i)
+    if (N->getOperand(i).getOpcode() != ISD::UNDEF) {
+      AllUndef = false;
+      break;
+    }
+
+  if (AllUndef)
+    return DAG.getUNDEF(N->getValueType(0));
+
   return SDValue();
 }
 

Added: llvm/trunk/test/CodeGen/X86/2012-07-10-shufnorm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-07-10-shufnorm.ll?rev=160221&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-07-10-shufnorm.ll (added)
+++ llvm/trunk/test/CodeGen/X86/2012-07-10-shufnorm.ll Sat Jul 14 16:30:27 2012
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86 -mcpu=corei7 -mattr=+avx | FileCheck %s
+
+; CHECK: ocl
+define void @ocl() {
+entry:
+  %vext = shufflevector <2 x double> zeroinitializer, <2 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %vecinit = shufflevector <8 x double> %vext, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %vecinit1 = insertelement <8 x double> %vecinit, double undef, i32 2
+  %vecinit3 = insertelement <8 x double> %vecinit1, double undef, i32 3
+  %vecinit5 = insertelement <8 x double> %vecinit3, double 0.000000e+00, i32 4
+  %vecinit9 = shufflevector <8 x double> %vecinit5, <8 x double> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 8, i32 9, i32 10>
+  store <8 x double> %vecinit9, <8 x double>* undef
+  ret void
+; CHECK: vxorps
+; CHECK: ret
+}
+