[llvm-commits] [llvm] r160101 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll

[Nick Lewycky]

Evan Cheng wrote:
> Author: evancheng
> Date: Wed Jul 11 20:45:35 2012
> New Revision: 160101
>
> URL: http://llvm.org/viewvc/llvm-project?rev=160101&view=rev
> Log:
> Instcombine was transforming:
>    %shr = lshr i64 %key, 3
>    %0 = load i64* %val, align 8
>    %sub = add i64 %0, -1
>    %and = and i64 %sub, %shr
>    ret i64 %and
>
> to:
>    %shr = lshr i64 %key, 3
>    %0 = load i64* %val, align 8
>    %sub = add i64 %0, 2305843009213693951
>    %and = and i64 %sub, %shr
>    ret i64 %and
>
> The demanded bit optimization is actually a pessimization because add -1 would
> be codegen'ed as a sub 1. Teach the demanded constant shrinking optimization
> to check for negated constant to make sure it is actually reducing the width
> of the constant.

I'm not a fan of this patch. Instead of just disabling the optz'n in 
this case, we should have some way to transform things into the '%sub = 
add i64 %0, -1' form, more generally.

Nick

>
> rdar://11793464
>
> Added:
>      llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll
> Modified:
>      llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
>
> Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=160101&r1=160100&r2=160101&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original)
> +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Wed Jul 11 20:45:35 2012
> @@ -40,6 +40,13 @@
>
>     // This instruction is producing bits that are not demanded. Shrink the RHS.
>     Demanded&= OpC->getValue();
> +  if (I->getOpcode() == Instruction::Add) {
> +    // However, if the instruction is an add then the constant may be negated
> +    // when the opcode is changed to sub. Check if the transformation is really
> +    // shrinking the constant.
> +    if (Demanded.abs().getActiveBits()>  OpC->getValue().abs().getActiveBits())
> +      return false;
> +  }
>     I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
>     return true;
>   }
>
> Added: llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll?rev=160101&view=auto
> ==============================================================================
> --- llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll (added)
> +++ llvm/trunk/test/Transforms/InstCombine/2012-07-11-AddSubDemandedBits.ll Wed Jul 11 20:45:35 2012
> @@ -0,0 +1,18 @@
> +; RUN: opt<  %s -instcombine -S | FileCheck %s
> +
> +; When shrinking demanded constant operand of an add instruction, keep in
> +; mind the opcode can be changed to sub and the constant negated. Make sure
> +; the shrinking the constant would actually reduce the width.
> +; rdar://11793464
> +
> +define i64 @t(i64 %key, i64* %val) nounwind {
> +entry:
> +; CHECK: @t
> +; CHECK-NOT: add i64 %0, 2305843009213693951
> +; CHECK: add i64 %0, -1
> +  %shr = lshr i64 %key, 3
> +  %0 = load i64* %val, align 8
> +  %sub = sub i64 %0, 1
> +  %and = and i64 %sub, %shr
> +  ret i64 %and
> +}
>
>
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