[llvm-commits] [llvm] r160069 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp

[Chad Rosier]

Author: mcrosier
Date: Wed Jul 11 14:58:38 2012
New Revision: 160069

URL: http://llvm.org/viewvc/llvm-project?rev=160069&view=rev
Log:
[x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose
comments.


Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=160069&r1=160068&r2=160069&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed Jul 11 14:58:38 2012
@@ -1693,7 +1693,6 @@
 
     // Promote the value if needed.
     switch (VA.getLocInfo()) {
-    default: return false;
     case CCValAssign::Full: break;
     case CCValAssign::SExt: {
       assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&
@@ -1737,6 +1736,14 @@
       ArgVT = VA.getLocVT();
       break;
     }
+    case CCValAssign::VExt: 
+      // VExt has not been implemented, so this should be impossible to reach
+      // for now.  However, fallback to Selection DAG isel once implemented.
+      return false;
+    case CCValAssign::Indirect:
+      // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully
+      // support this.
+      return false;
     }
 
     if (VA.isRegLoc()) {