[llvm-commits] [llvm] r160044 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2012-07-10-extload64.ll test/CodeGen/X86/mmx-punpckhdq.ll test/CodeGen/X86/pointer-vector.ll test/CodeGen/X86/widen_cast-1.ll test/CodeGen/X86/widen_cast-5.ll
Nadav Rotem
nadav.rotem at intel.com
Wed Jul 11 06:27:05 PDT 2012
Author: nadav
Date: Wed Jul 11 08:27:05 2012
New Revision: 160044
URL: http://llvm.org/viewvc/llvm-project?rev=160044&view=rev
Log:
When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers.
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll
llvm/trunk/test/CodeGen/X86/mmx-punpckhdq.ll
llvm/trunk/test/CodeGen/X86/pointer-vector.ll
llvm/trunk/test/CodeGen/X86/widen_cast-1.ll
llvm/trunk/test/CodeGen/X86/widen_cast-5.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jul 11 08:27:05 2012
@@ -14464,6 +14464,11 @@
}
}
+ // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
+ if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 &&
+ (64 <= MemSz))
+ SclrLoadTy = MVT::f64;
+
// Calculate the number of scalar loads that we need to perform
// in order to load our vector from memory.
unsigned NumLoads = MemSz / SclrLoadTy.getSizeInBits();
@@ -14615,13 +14620,18 @@
for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
MVT Tp = (MVT::SimpleValueType)tp;
- if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz)
+ if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToSz)
StoreType = Tp;
}
+ // On 32bit systems, we can't save 64bit integers. Try bitcasting to F64.
+ if (TLI.isTypeLegal(MVT::f64) && StoreType.getSizeInBits() < 64 &&
+ (64 <= NumElems * ToSz))
+ StoreType = MVT::f64;
+
// Bitcast the original vector into a vector of store-size units
EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
- StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
+ StoreType, VT.getSizeInBits()/StoreType.getSizeInBits());
assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);
SmallVector<SDValue, 8> Chains;
Modified: llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2012-07-10-extload64.ll Wed Jul 11 08:27:05 2012
@@ -3,11 +3,30 @@
; CHECK: load_store
define void @load_store(<4 x i16>* %in) {
entry:
+; CHECK: movsd
%A27 = load <4 x i16>* %in, align 4
%A28 = add <4 x i16> %A27, %A27
+; CHECK: movlpd
store <4 x i16> %A28, <4 x i16>* %in, align 4
ret void
-; CHECK: movd
-; CHECK: pinsrd
; CHECK: ret
}
+
+; Make sure that we store a 64bit value, even on 32bit systems.
+;CHECK: store_64
+define void @store_64(<2 x i32>* %ptr) {
+BB:
+ store <2 x i32> zeroinitializer, <2 x i32>* %ptr
+ ret void
+;CHECK: movlpd
+;CHECK: ret
+}
+
+;CHECK: load_64
+define <2 x i32> @load_64(<2 x i32>* %ptr) {
+BB:
+ %t = load <2 x i32>* %ptr
+ ret <2 x i32> %t
+;CHECK: movsd
+;CHECK: ret
+}
Modified: llvm/trunk/test/CodeGen/X86/mmx-punpckhdq.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-punpckhdq.ll?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-punpckhdq.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-punpckhdq.ll Wed Jul 11 08:27:05 2012
@@ -3,7 +3,7 @@
define void @bork(<1 x i64>* %x) {
; CHECK: bork
-; CHECK: pextrd
+; CHECK: movlpd
entry:
%tmp2 = load <1 x i64>* %x ; <<1 x i64>> [#uses=1]
%tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32> ; <<2 x i32>> [#uses=1]
Modified: llvm/trunk/test/CodeGen/X86/pointer-vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pointer-vector.ll?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pointer-vector.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pointer-vector.ll Wed Jul 11 08:27:05 2012
@@ -105,8 +105,7 @@
entry:
%G = load <2 x i8*>* %p
;CHECK: movl
-;CHECK: movd
-;CHECK: pinsrd
+;CHECK: movsd
%T = bitcast <2 x i8*> %G to <2 x i32*>
;CHECK: ret
ret <2 x i32*> %T
Modified: llvm/trunk/test/CodeGen/X86/widen_cast-1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-1.ll?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_cast-1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_cast-1.ll Wed Jul 11 08:27:05 2012
@@ -1,7 +1,7 @@
; RUN: llc -march=x86 -mattr=+sse42 < %s | FileCheck %s
; CHECK: paddd
-; CHECK: pextrd
-; CHECK: movd
+; CHECK: movl
+; CHECK: movlpd
; bitcast a v4i16 to v2i32
Modified: llvm/trunk/test/CodeGen/X86/widen_cast-5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_cast-5.ll?rev=160044&r1=160043&r2=160044&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/widen_cast-5.ll (original)
+++ llvm/trunk/test/CodeGen/X86/widen_cast-5.ll Wed Jul 11 08:27:05 2012
@@ -1,9 +1,8 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s
; CHECK: movl
-; CHECK: movd
+; CHECK: movlpd
; bitcast a i64 to v2i32
-
define void @convert(<2 x i32>* %dst.addr, i64 %src) nounwind {
entry:
%conv = bitcast i64 %src to <2 x i32>
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