[llvm-commits] [llvm] r159938 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/ARM/simple-fp-encoding.s
Chad Rosier
mcrosier at apple.com
Tue Jul 10 09:48:42 PDT 2012
On Jul 10, 2012, at 5:57 AM, Richard Barton wrote:
> Hi Chad
>
> I've had a bit of a shocker. I fixed the tests in my working copy, then forgot to commit the changes.
>
> I have also noticed that my fix on the original 'fix' was not complete. As I clearly did not test the disassembly properly, I took a step back, added some new regression tests for my fix, and got them all to pass.
>
> I'm confident that r159989 should be good. I guess we will find out from the build bots in due course. Sorry for the breakage and thanks for reverting my original bad changes.
Great. Thanks, Rich.
Chad
> Ta
> Rich
>
>> -----Original Message-----
>> From: Chad Rosier [mailto:mcrosier at apple.com]
>> Sent: 09 July 2012 20:34
>> To: Richard Barton
>> Cc: llvm-commits at cs.uiuc.edu
>> Subject: Re: [llvm-commits] [llvm] r159938 - in /llvm/trunk:
>> lib/Target/ARM/ARMInstrVFP.td lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>> test/MC/ARM/simple-fp-encoding.s
>>
>> Richard,
>> Looks like this isn't quite fixed; the register names are not matching.
>>
>>
>> --
>> llvm/test/MC/Disassembler/ARM/neon.txt:1898:10: error: expected string not
>> found in input
>> # CHECK: vmovvs r2, lr, s29, s30
>> ^
>> <stdin>:897:2: note: scanning from here
>> vmovvs r2, lr, s27, s28
>> ^
>> --
>> Chad
>>
>>
>> On Jul 9, 2012, at 11:23 AM, Chad Rosier wrote:
>>
>>
>>
>> On Jul 9, 2012, at 11:22 AM, Richard Barton wrote:
>>
>>
>>
>> Hi Chad
>>
>>
>>
>> My change completely broke disassembling the VMOV Rt, Rt2, Sm,
>> Sm+1 instruction.
>>
>>
>> I must not have run the full test suite over it - must do better!
>>
>>
>>
>> Have committed a fix: r159945. Sorry for the breakage.
>>
>>
>>
>> Thanks for the quick fix!
>>
>> Chad
>>
>>
>>
>> Rich
>>
>>
>>
>> -----Original Message-----
>>
>>
>> From: Chad Rosier [mailto:mcrosier at apple.com]
>>
>>
>> Sent: 09 July 2012 19:02
>>
>>
>> To: Richard Barton
>>
>>
>> Cc: llvm-commits at cs.uiuc.edu
>>
>>
>> Subject: Re: [llvm-commits] [llvm] r159938 - in /llvm/trunk:
>>
>>
>> lib/Target/ARM/ARMInstrVFP.td
>> lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>
>>
>> test/MC/ARM/simple-fp-encoding.s
>>
>>
>>
>> Richard,
>>
>>
>> This appears to be causing failures on our internal builders
>> with the
>>
>>
>> following warnings:
>>
>>
>>
>> ******************** TEST 'LLVM ::
>> MC/Disassembler/ARM/neon.txt' FAILED
>>
>>
>> ********************Script:
>>
>>
>> --
>>
>>
>> 0xa4 0x0d 0xa3 0xf4
>>
>>
>> ^
>>
>>
>> llvm/test/MC/Disassembler/ARM/neon.txt:1898:10: error:
>> expected string not
>>
>>
>> found in input
>>
>>
>> # CHECK: vmovvs r2, lr, s29, s30
>>
>>
>> ^
>>
>>
>> <stdin>:897:2: note: scanning from here
>>
>>
>> stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^
>>
>>
>> ^
>>
>>
>> <stdin>:897:11: note: possible intended match here
>>
>>
>> stmdb r12!, {r1, r3, r5, r9, r10, r11, r12, lr} ^
>>
>>
>> ^
>>
>>
>> --
>>
>>
>>
>> ********************
>>
>>
>>
>> Chad
>>
>>
>>
>> On Jul 9, 2012, at 9:41 AM, Richard Barton wrote:
>>
>>
>>
>>
>> Author: rbarton
>>
>>
>> Date: Mon Jul 9 11:41:33 2012
>>
>>
>> New Revision: 159938
>>
>>
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=159938&view=rev
>>
>>
>> Log:
>>
>>
>> Fix instruction description of VMOV (between two ARM core
>> registers and
>>
>>
>> two single-precision resiters)
>>
>>
>>
>> Modified:
>>
>>
>> llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>>
>>
>> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>
>>
>> llvm/trunk/test/MC/ARM/simple-fp-encoding.s
>>
>>
>>
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td
>>
>>
>> URL: http://llvm.org/viewvc/llvm-
>>
>>
>>
>> project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=159938&r1=159937&r2
>> =15993
>>
>>
>> 8&view=diff
>>
>>
>>
>> ========================================================================
>>
>>
>> ======
>>
>>
>> --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original)
>>
>>
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Jul 9
>> 11:41:33 2012
>>
>>
>> @@ -567,8 +567,8 @@
>>
>>
>> bits<4> Rt2;
>>
>>
>>
>> // Encode instruction operands.
>>
>>
>> - let Inst{3-0} = src1{3-0};
>>
>>
>> - let Inst{5} = src1{4};
>>
>>
>> + let Inst{3-0} = src1{4-1};
>>
>>
>> + let Inst{5} = src1{0};
>>
>>
>> let Inst{15-12} = Rt;
>>
>>
>> let Inst{19-16} = Rt2;
>>
>>
>>
>> @@ -617,8 +617,8 @@
>>
>>
>> bits<4> src2;
>>
>>
>>
>> // Encode instruction operands.
>>
>>
>> - let Inst{3-0} = dst1{3-0};
>>
>>
>> - let Inst{5} = dst1{4};
>>
>>
>> + let Inst{3-0} = dst1{4-1};
>>
>>
>> + let Inst{5} = dst1{0};
>>
>>
>> let Inst{15-12} = src1;
>>
>>
>> let Inst{19-16} = src2;
>>
>>
>>
>>
>> Modified:
>> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>
>>
>> URL: http://llvm.org/viewvc/llvm-
>>
>>
>>
>> project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=1
>> 59938&
>>
>>
>> r1=159937&r2=159938&view=diff
>>
>>
>>
>> ========================================================================
>>
>>
>> ======
>>
>>
>> ---
>> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
>>
>>
>> (original)
>>
>>
>> +++
>> llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Mon Jul
>>
>>
>> 9 11:41:33 2012
>>
>>
>> @@ -4198,9 +4198,9 @@
>>
>>
>> DecodeStatus S = MCDisassembler::Success;
>>
>>
>> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
>>
>>
>> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
>>
>>
>> - unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>>
>>
>> + unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
>>
>>
>> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>>
>>
>> - Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
>>
>>
>> + Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
>>
>>
>>
>> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
>>
>>
>> S = MCDisassembler::SoftFail;
>>
>>
>> @@ -4224,9 +4224,9 @@
>>
>>
>> DecodeStatus S = MCDisassembler::Success;
>>
>>
>> unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
>>
>>
>> unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
>>
>>
>> - unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
>>
>>
>> + unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
>>
>>
>> unsigned pred = fieldFromInstruction32(Insn, 28, 4);
>>
>>
>> - Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
>>
>>
>> + Rm |= fieldFromInstruction32(Insn, 0, 4) << 4;
>>
>>
>>
>> if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
>>
>>
>> S = MCDisassembler::SoftFail;
>>
>>
>>
>> Modified: llvm/trunk/test/MC/ARM/simple-fp-encoding.s
>>
>>
>> URL: http://llvm.org/viewvc/llvm-
>> project/llvm/trunk/test/MC/ARM/simple-
>>
>>
>> fp-encoding.s?rev=159938&r1=159937&r2=159938&view=diff
>>
>>
>>
>> ========================================================================
>>
>>
>> ======
>>
>>
>> --- llvm/trunk/test/MC/ARM/simple-fp-encoding.s (original)
>>
>>
>> +++ llvm/trunk/test/MC/ARM/simple-fp-encoding.s Mon Jul 9
>> 11:41:33 2012
>>
>>
>> @@ -196,6 +196,27 @@
>>
>>
>> @ CHECK: vmov r0, r1, d16 @ encoding:
>> [0x30,0x0b,0x51,0xec]
>>
>>
>> vmov r0, r1, d16
>>
>>
>>
>> +@ Between two single precision registers and two core
>> registers
>>
>>
>> + vmov s3, s4, r1, r2
>>
>>
>> + vmov s2, s3, r1, r2
>>
>>
>> + vmov r1, r2, s3, s4
>>
>>
>> + vmov r1, r2, s2, s3
>>
>>
>> +@ CHECK: vmov s3, s4, r1, r2 @ encoding:
>> [0x31,0x1a,0x42,0xec]
>>
>>
>> +@ CHECK: vmov s2, s3, r1, r2 @ encoding:
>> [0x11,0x1a,0x42,0xec]
>>
>>
>> +@ CHECK: vmov r1, r2, s3, s4 @ encoding:
>> [0x31,0x1a,0x52,0xec]
>>
>>
>> +@ CHECK: vmov r1, r2, s2, s3 @ encoding:
>> [0x11,0x1a,0x52,0xec]
>>
>>
>> +
>>
>>
>> +@ Between one double precision register and two core
>> registers
>>
>>
>> + vmov d15, r1, r2
>>
>>
>> + vmov d16, r1, r2
>>
>>
>> + vmov r1, r2, d15
>>
>>
>> + vmov r1, r2, d16
>>
>>
>> +@ CHECK: vmov d15, r1, r2 @ encoding:
>> [0x1f,0x1b,0x42,0xec]
>>
>>
>> +@ CHECK: vmov d16, r1, r2 @ encoding:
>> [0x30,0x1b,0x42,0xec]
>>
>>
>> +@ CHECK: vmov r1, r2, d15 @ encoding:
>> [0x1f,0x1b,0x52,0xec]
>>
>>
>> +@ CHECK: vmov r1, r2, d16 @ encoding:
>> [0x30,0x1b,0x52,0xec]
>>
>>
>> +
>>
>>
>> +
>>
>>
>> @ CHECK: vldr d17, [r0] @ encoding:
>> [0x00,0x1b,0xd0,0xed]
>>
>>
>> @ CHECK: vldr s0, [lr] @ encoding:
>> [0x00,0x0a,0x9e,0xed]
>>
>>
>> @ CHECK: vldr d0, [lr] @ encoding:
>> [0x00,0x0b,0x9e,0xed]
>>
>>
>>
>>
>> _______________________________________________
>>
>>
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>>
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