[llvm-commits] [llvm] r159694 - in /llvm/trunk: include/llvm/CodeGen/Passes.h include/llvm/InitializePasses.h include/llvm/Target/TargetInstrInfo.h lib/CodeGen/CMakeLists.txt lib/CodeGen/CodeGen.cpp lib/CodeGen/EarlyIfConversion.cpp lib/CodeGen/Passes

[Sergei Larin]

Jakob,

 

  This is rather interesting for our target as well. Thank you for working
on this.

 

Sergei

 

--

Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum.

 

From: llvm-commits-bounces at cs.uiuc.edu
[mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Jakob Stoklund Olesen
Sent: Tuesday, July 03, 2012 8:13 PM
To: Hal Finkel
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r159694 - in /llvm/trunk:
include/llvm/CodeGen/Passes.h include/llvm/InitializePasses.h
include/llvm/Target/TargetInstrInfo.h lib/CodeGen/CMakeLists.txt
lib/CodeGen/CodeGen.cpp lib/CodeGen/EarlyIfConversion.cpp lib/CodeGen/Passes

 

 

On Jul 3, 2012, at 5:26 PM, Hal Finkel <hfinkel at anl.gov> wrote:





Add an experimental early if-conversion pass, off by default.


Cool. I can probably use this on PPC as well.

 

I expect you can.





How does this differ from CodeGen/IfConversion.cpp?

 

The late if-conversion pass uses predication, so it only works on
architectures like ARM that can predicate most instructions. The predication
means that the pass can run after register allocation, it will never
increase register pressure.

 

The early if-conversion pass will speculatively execute both sides of a
branch, and then insert a select instruction to choose the result. It only
really makes sense for out-of-order CPUs where the speculated instructions
can be hidden as extra ILP.

 

The TBD heuristics will assume an out-of-order super-scalar CPU, but I
suppose an in-order super-scalar micro-architecture can benefit as well once
Andy's MI scheduler is up and running.

 

/jakob

 

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