[llvm-commits] [llvm] r159176 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll test/CodeGen/X86/asm-reg-type-mismatch.ll

[Eli Friedman]

Author: efriedma
Date: Mon Jun 25 18:42:33 2012
New Revision: 159176

URL: http://llvm.org/viewvc/llvm-project?rev=159176&view=rev
Log:
Make some ugly hacks for inline asm operands which name a specific register a bit more thorough.  PR13196.


Added:
    llvm/trunk/test/CodeGen/X86/asm-reg-type-mismatch.ll
      - copied, changed from r159158, llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Removed:
    llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=159176&r1=159175&r2=159176&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jun 25 18:42:33 2012
@@ -16030,12 +16030,15 @@
     // wrong class.  This can happen with constraints like {xmm0} where the
     // target independent register mapper will just pick the first match it can
     // find, ignoring the required type.
-    if (VT == MVT::f32)
+
+    if (VT == MVT::f32 || VT == MVT::i32)
       Res.second = &X86::FR32RegClass;
-    else if (VT == MVT::f64)
+    else if (VT == MVT::f64 || VT == MVT::i64)
       Res.second = &X86::FR64RegClass;
     else if (X86::VR128RegClass.hasType(VT))
       Res.second = &X86::VR128RegClass;
+    else if (X86::VR256RegClass.hasType(VT))
+      Res.second = &X86::VR256RegClass;
   }
 
   return Res;

Removed: llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll?rev=159175&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (removed)
@@ -1,18 +0,0 @@
-; RUN: llc < %s -mcpu=core2 | grep xorps | count 2
-; RUN: llc < %s -mcpu=core2 | not grep movap
-; PR2715
-
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
-target triple = "x86_64-unknown-linux-gnu"
-	%struct.XPTTypeDescriptorPrefix = type { i8 }
-	%struct.nsISupports = type { i32 (...)** }
-	%struct.nsXPTCMiniVariant = type { %"struct.nsXPTCMiniVariant::._39" }
-	%"struct.nsXPTCMiniVariant::._39" = type { i64 }
-	%struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
-	%struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
-
-define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
-entry:
-	call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
-	ret i32 0
-}

Copied: llvm/trunk/test/CodeGen/X86/asm-reg-type-mismatch.ll (from r159158, llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/asm-reg-type-mismatch.ll?p2=llvm/trunk/test/CodeGen/X86/asm-reg-type-mismatch.ll&p1=llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll&r1=159158&r2=159176&rev=159176&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-25-AsmRegTypeMismatch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/asm-reg-type-mismatch.ll Mon Jun 25 18:42:33 2012
@@ -1,5 +1,4 @@
-; RUN: llc < %s -mcpu=core2 | grep xorps | count 2
-; RUN: llc < %s -mcpu=core2 | not grep movap
+; RUN: llc < %s -mcpu=core2 | FileCheck %s
 ; PR2715
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
@@ -11,8 +10,22 @@
 	%struct.nsXPTCVariant = type { %struct.nsXPTCMiniVariant, i8*, %struct.nsXPTType, i8 }
 	%struct.nsXPTType = type { %struct.XPTTypeDescriptorPrefix }
 
-define i32 @XPTC_InvokeByIndex(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
+define i32 @test1(%struct.nsISupports* %that, i32 %methodIndex, i32 %paramCount, %struct.nsXPTCVariant* %params) nounwind {
 entry:
 	call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},~{dirflag},~{fpsr},~{flags}"( double undef, double undef, double undef, double 1.0, double undef, double 0.0, double undef, double 0.0 ) nounwind
 	ret i32 0
+	; CHECK: test1
+	; CHECK-NOT: movap
+	; CHECK: xorps
+	; CHECK: xorps
+	; CHECK-NOT: movap
+}
+
+define i64 @test2() nounwind {
+entry:
+  %0 = tail call i64 asm sideeffect "movq $1, $0", "={xmm7},*m,~{dirflag},~{fpsr},~{flags}"(i64* null) nounwind
+  ret i64 %0
+  ; CHECK: test2
+	; CHECK: movq {{.*}}, %xmm7
+	; CHECK: movd %xmm7, %rax
 }