[llvm-commits] [llvm] r159086 - in /llvm/trunk/lib/Target/X86: X86InstrFormats.td X86InstrSSE.td
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Sat Jun 23 14:23:26 PDT 2012
Can't you write a llvm-mc (e.g. assembler) based test that checks for
a specific processor feature?
On Sat, Jun 23, 2012 at 5:52 PM, Craig Topper <craig.topper at gmail.com> wrote:
> I can't write a test case because the instructions themselves don't have
> patterns declared in them.
>
>
> On Sat, Jun 23, 2012 at 1:29 PM, Bruno Cardoso Lopes
> <bruno.cardoso at gmail.com> wrote:
>>
>> Hi Craig,
>>
>> Testcase?
>>
>> On Sat, Jun 23, 2012 at 5:15 PM, Craig Topper <craig.topper at gmail.com>
>> wrote:
>> > Author: ctopper
>> > Date: Sat Jun 23 15:15:42 2012
>> > New Revision: 159086
>> >
>> > URL: http://llvm.org/viewvc/llvm-project?rev=159086&view=rev
>> > Log:
>> > Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and
>> > PD2DQ to the SSE2 section of the file.
>> >
>> > Modified:
>> > llvm/trunk/lib/Target/X86/X86InstrFormats.td
>> > llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> >
>> > Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=159086&r1=159085&r2=159086&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
>> > +++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Sat Jun 23 15:15:42
>> > 2012
>> > @@ -366,6 +366,7 @@
>> > //
>> > // SDI - SSE2 instructions with XD prefix.
>> > // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
>> > +// SSDI - SSE2 instructions with XD prefix.
>> > // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
>> > // PDI - SSE2 instructions with TB and OpSize prefixes.
>> > // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize
>> > prefixes.
>> >
>> > Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
>> > URL:
>> > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=159086&r1=159085&r2=159086&view=diff
>> >
>> > ==============================================================================
>> > --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
>> > +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sat Jun 23 15:15:42 2012
>> > @@ -1855,6 +1855,36 @@
>> > (memop addr:$src)))],
>> > IIC_SSE_CVT_PS_RM>;
>> >
>> > +// Convert Packed Double FP to Packed DW Integers
>> > +let Predicates = [HasAVX] in {
>> > +// The assembler can recognize rr 256-bit instructions by seeing a ymm
>> > +// register, but the same isn't true when using memory operands
>> > instead.
>> > +// Provide other assembly rr and rm forms to address this explicitly.
>> > +def VCVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > + "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +def VCVTPD2DQXrYr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR256:$src),
>> > + "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>,
>> > VEX;
>> > +
>> > +// XMM only
>> > +def VCVTPD2DQXrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +def VCVTPD2DQXrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f128mem:$src),
>> > + "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +
>> > +// YMM only
>> > +def VCVTPD2DQYrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR256:$src),
>> > + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,
>> > VEX;
>> > +def VCVTPD2DQYrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f256mem:$src),
>> > + "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,
>> > VEX, VEX_L;
>> > +}
>> > +
>> > +def CVTPD2DQrm : SDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f128mem:$src),
>> > + "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
>> > + IIC_SSE_CVT_PD_RM>;
>> > +def CVTPD2DQrr : SDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > + "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
>> > + IIC_SSE_CVT_PD_RR>;
>> > +
>> > // SSE2 packed instructions with XD prefix
>> > def Int_VCVTPD2DQrr : I<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > "vcvtpd2dq\t{$src, $dst|$dst, $src}",
>> > @@ -1992,6 +2022,13 @@
>> > "cvttpd2dq{y}\t{$src, $dst|$dst, $src}", [],
>> > IIC_SSE_CVT_PD_RM>, VEX, VEX_L;
>> >
>> > +let Predicates = [HasAVX] in {
>> > + def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
>> > + (VCVTTPD2DQYrr VR256:$src)>;
>> > + def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
>> > + (VCVTTPD2DQYrm addr:$src)>;
>> > +} // Predicates = [HasAVX]
>> > +
>> > // Convert packed single to packed double
>> > let Predicates = [HasAVX] in {
>> > // SSE2 instructions without OpSize prefix
>> > @@ -2038,6 +2075,52 @@
>> > IIC_SSE_CVT_PD_RM>,
>> > TB, Requires<[HasSSE2]>;
>> >
>> > +// Convert Packed DW Integers to Packed Double FP
>> > +let Predicates = [HasAVX] in {
>> > +def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > i64mem:$src),
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins
>> > i128mem:$src),
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins
>> > VR128:$src),
>> > + "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > +}
>> > +
>> > +def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > i64mem:$src),
>> > + "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
>> > + IIC_SSE_CVT_PD_RR>;
>> > +def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > + "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
>> > + IIC_SSE_CVT_PD_RM>;
>> > +
>> > +// 128 bit register conversion intrinsics
>> > +let Predicates = [HasAVX] in
>> > +def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
>> > + (VCVTDQ2PDrr VR128:$src)>;
>> > +
>> > +let Predicates = [HasSSE2] in
>> > +def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
>> > + (CVTDQ2PDrr VR128:$src)>;
>> > +
>> > +// AVX 256-bit register conversion intrinsics
>> > +let Predicates = [HasAVX] in {
>> > + def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
>> > + (VCVTDQ2PDYrr VR128:$src)>;
>> > + def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64
>> > addr:$src))),
>> > + (VCVTDQ2PDYrm addr:$src)>;
>> > +
>> > + def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
>> > + (VCVTPD2DQYrr VR256:$src)>;
>> > + def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
>> > + (VCVTPD2DQYrm addr:$src)>;
>> > +
>> > + def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
>> > + (VCVTDQ2PDYrr VR128:$src)>;
>> > + def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
>> > + (VCVTDQ2PDYrm addr:$src)>;
>> > +} // Predicates = [HasAVX]
>> > +
>> > // Convert packed double to packed single
>> > // The assembler can recognize rr 256-bit instructions by seeing a ymm
>> > // register, but the same isn't true when using memory operands
>> > instead.
>> > @@ -4867,93 +4950,6 @@
>> > "movq\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVQ_RR>,
>> > XS;
>> >
>> >
>> > //===---------------------------------------------------------------------===//
>> > -// SSE3 - Conversion Instructions
>> >
>> > -//===---------------------------------------------------------------------===//
>> > -
>> > -// Convert Packed Double FP to Packed DW Integers
>> > -let Predicates = [HasAVX] in {
>> > -// The assembler can recognize rr 256-bit instructions by seeing a ymm
>> > -// register, but the same isn't true when using memory operands
>> > instead.
>> > -// Provide other assembly rr and rm forms to address this explicitly.
>> > -def VCVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > - "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -def VCVTPD2DQXrYr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR256:$src),
>> > - "vcvtpd2dq\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -
>> > -// XMM only
>> > -def VCVTPD2DQXrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -def VCVTPD2DQXrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f128mem:$src),
>> > - "vcvtpd2dqx\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -
>> > -// YMM only
>> > -def VCVTPD2DQYrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR256:$src),
>> > - "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,
>> > VEX;
>> > -def VCVTPD2DQYrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f256mem:$src),
>> > - "vcvtpd2dq{y}\t{$src, $dst|$dst, $src}", []>,
>> > VEX, VEX_L;
>> > -}
>> > -
>> > -def CVTPD2DQrm : S3DI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > f128mem:$src),
>> > - "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
>> > - IIC_SSE_CVT_PD_RM>;
>> > -def CVTPD2DQrr : S3DI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > - "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
>> > - IIC_SSE_CVT_PD_RR>;
>> > -
>> > -let Predicates = [HasAVX] in {
>> > - def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
>> > - (VCVTTPD2DQYrr VR256:$src)>;
>> > - def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
>> > - (VCVTTPD2DQYrm addr:$src)>;
>> > -} // Predicates = [HasAVX]
>> > -
>> > -// Convert Packed DW Integers to Packed Double FP
>> > -let Predicates = [HasAVX] in {
>> > -def VCVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > i64mem:$src),
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -def VCVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -def VCVTDQ2PDYrm : SSDI<0xE6, MRMSrcMem, (outs VR256:$dst), (ins
>> > i128mem:$src),
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -def VCVTDQ2PDYrr : SSDI<0xE6, MRMSrcReg, (outs VR256:$dst), (ins
>> > VR128:$src),
>> > - "vcvtdq2pd\t{$src, $dst|$dst, $src}", []>, VEX;
>> > -}
>> > -
>> > -def CVTDQ2PDrm : SSDI<0xE6, MRMSrcMem, (outs VR128:$dst), (ins
>> > i64mem:$src),
>> > - "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
>> > - IIC_SSE_CVT_PD_RR>;
>> > -def CVTDQ2PDrr : SSDI<0xE6, MRMSrcReg, (outs VR128:$dst), (ins
>> > VR128:$src),
>> > - "cvtdq2pd\t{$src, $dst|$dst, $src}", [],
>> > - IIC_SSE_CVT_PD_RM>;
>> > -
>> > -// 128 bit register conversion intrinsics
>> > -let Predicates = [HasAVX] in
>> > -def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
>> > - (VCVTDQ2PDrr VR128:$src)>;
>> > -
>> > -let Predicates = [HasSSE2] in
>> > -def : Pat<(int_x86_sse2_cvtdq2pd VR128:$src),
>> > - (CVTDQ2PDrr VR128:$src)>;
>> > -
>> > -// AVX 256-bit register conversion intrinsics
>> > -let Predicates = [HasAVX] in {
>> > - def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
>> > - (VCVTDQ2PDYrr VR128:$src)>;
>> > - def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64
>> > addr:$src))),
>> > - (VCVTDQ2PDYrm addr:$src)>;
>> > -
>> > - def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
>> > - (VCVTPD2DQYrr VR256:$src)>;
>> > - def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
>> > - (VCVTPD2DQYrm addr:$src)>;
>> > -
>> > - def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
>> > - (VCVTDQ2PDYrr VR128:$src)>;
>> > - def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
>> > - (VCVTDQ2PDYrm addr:$src)>;
>> > -} // Predicates = [HasAVX]
>> > -
>> >
>> > -//===---------------------------------------------------------------------===//
>> > // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
>> >
>> > //===---------------------------------------------------------------------===//
>> > multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string
>> > OpcodeStr,
>> >
>> >
>> > _______________________________________________
>> > llvm-commits mailing list
>> > llvm-commits at cs.uiuc.edu
>> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>>
>> --
>> Bruno Cardoso Lopes
>> http://www.brunocardoso.cc
>
>
>
>
> --
> ~Craig
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
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