[llvm-commits] [PATCH] X86: Add support for GATHER intrinsics of X86 AVX2, please review

[Manman Ren]

Support the following intrinsics:
  _mm_mask_i32gather_pd, _mm256_mask_i32gather_pd, _mm_mask_i64gather_pd
  _mm256_mask_i64gather_pd, _mm_mask_i32gather_ps, _mm256_mask_i32gather_ps
  _mm_mask_i64gather_ps, _mm256_mask_i64gather_ps

There are two places which I am not sure about:
1> Is a customized ISel needed for GATHER?
   I can't figure out how to select the address operands for GATHER intrinsics
   in a .td file, given that index and scale are passed in as parameters.
   gather(<2 x double> %a0, i8* %base, <2 x i64> %idx, <2 x double> %mask, i8 scale) 

2> Is there a better way to modify disassembler to handle VSIB addressing mode?
   The existing disassembler assumes index register is encoded for SIB only.
   However VSIB has a different mapping for the index registers.
   For example: index field of 100 means VR4 or VR12 for VSIB, and it means
                no index register for SIB.
   We don't know whether it is VSIB or SIB before the instruction ID is decoded.
   It looks to me that X86::VGATHER is not exposed to readSIB in X86DisassemblerDecoder.c
   The attached patch checks whether it is VSIB during translation and if yes,
   it will update index register to the correct value according to VSIB.

File modified:
test/MC/X86/x86_64-avx-encoding.s
test/MC/Disassembler/X86/simple-tests.txt
test/CodeGen/X86/avx2-intrinsics-x86.ll
include/llvm/IntrinsicsX86.td
utils/TableGen/EDEmitter.cpp
utils/TableGen/X86RecognizableInstr.cpp
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/AsmParser/X86AsmParser.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86InstrSSE.td
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
lib/Target/X86/Disassembler/X86DisassemblerDecoder.h
lib/Target/X86/Disassembler/X86Disassembler.cpp

Comments are appreciated.

Thanks,
Manman
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