[llvm-commits] [llvm] r158960 - /llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

[Andrew Trick]

Author: atrick
Date: Thu Jun 21 21:50:33 2012
New Revision: 158960

URL: http://llvm.org/viewvc/llvm-project?rev=158960&view=rev
Log:
ARM scheduling fix: don't guess at implicit operand latency.

This is a minor drive-by fix with no robust way to unit test.
As an example see neon-div.ll:
SU(16):   %Q8<def> = VMOVLsv4i32 %D17, pred:14, pred:%noreg, %Q8<imp-use,kill>
 val SU(1): Latency=2 Reg=%Q8
...should be latency=1

Modified:
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=158960&r1=158959&r2=158960&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Thu Jun 21 21:50:33 2012
@@ -2746,11 +2746,12 @@
     unsigned NewUseIdx;
     const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
                                                    Reg, NewUseIdx, UseAdj);
-    if (NewUseMI) {
-      UseMI = NewUseMI;
-      UseIdx = NewUseIdx;
-      UseMCID = &UseMI->getDesc();
-    }
+    if (!NewUseMI)
+      return -1;
+
+    UseMI = NewUseMI;
+    UseIdx = NewUseIdx;
+    UseMCID = &UseMI->getDesc();
   }
 
   if (Reg == ARM::CPSR) {
@@ -2778,6 +2779,9 @@
     return Latency;
   }
 
+  if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
+    return -1;
+
   unsigned DefAlign = DefMI->hasOneMemOperand()
     ? (*DefMI->memoperands_begin())->getAlignment() : 0;
   unsigned UseAlign = UseMI->hasOneMemOperand()