[llvm-commits] [llvm] r158935 - in /llvm/trunk: lib/Target/Mips/Mips16InstrInfo.td lib/Target/Mips/MipsFrameLowering.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/null.ll
Akira Hatanaka
ahatanaka at mips.com
Thu Jun 21 13:39:10 PDT 2012
Author: ahatanak
Date: Thu Jun 21 15:39:10 2012
New Revision: 158935
URL: http://llvm.org/viewvc/llvm-project?rev=158935&view=rev
Log:
1. fix null program output after some other changes
2. re-enable null.ll test
3. fix some minor style violations
Patch by Reed Kotler.
Modified:
llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/Mips/null.ll
Modified: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td?rev=158935&r1=158934&r2=158935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td Thu Jun 21 15:39:10 2012
@@ -11,19 +11,29 @@
//
//===----------------------------------------------------------------------===//
+class Mips16Pat<dag pattern, dag result> : Pat<pattern, result> {
+ let Predicates = [InMips16Mode];
+}
+
+def LI16E : FEXT_RI16<0b01101, (outs CPU16Regs:$rx),
+ (ins uimm16:$amt),
+ !strconcat("li", "\t$rx, $amt"),
+ [(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>;
+
let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in
-def RET16 : FRR16_JALRC < (outs), (ins CPURAReg:$target),
- "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
+def RET16 : FRR16_JALRC
+ < (outs), (ins CPURAReg:$target),
+ "jr\t$target", [(MipsRet CPURAReg:$target)], IIBranch>;
// As stack alignment is always done with addiu, we need a 16-bit immediate
let Defs = [SP], Uses = [SP] in {
def ADJCALLSTACKDOWN16 : MipsPseudo16<(outs), (ins uimm16:$amt),
- "!ADJCALLSTACKDOWN $amt",
- [(callseq_start timm:$amt)]>;
+ "!ADJCALLSTACKDOWN $amt",
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
- "!ADJCALLSTACKUP $amt1",
- [(callseq_end timm:$amt1, timm:$amt2)]>;
+ "!ADJCALLSTACKUP $amt1",
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
@@ -31,4 +41,7 @@
let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
def JumpLinkReg16:
FRR16_JALRC<(outs), (ins CPU16Regs:$rs, variable_ops),
- "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+ "jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
+
+// Small immediates
+def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>;
Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=158935&r1=158934&r2=158935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Thu Jun 21 15:39:10 2012
@@ -112,7 +112,8 @@
// First, compute final stack size.
unsigned StackAlign = getStackAlignment();
- uint64_t StackSize = MFI->getObjectOffset(MipsFI->getGlobalRegFI()) +
+ uint64_t StackSize = STI.inMips16Mode()? 0:
+ MFI->getObjectOffset(MipsFI->getGlobalRegFI()) +
StackAlign + RoundUpToAlignment(MFI->getStackSize(), StackAlign);
// Update stack size
Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=158935&r1=158934&r2=158935&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Thu Jun 21 15:39:10 2012
@@ -125,7 +125,10 @@
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
- int FI = MipsFI->initGlobalRegFI();
+ int FI; // should initialize this to some kind of null
+
+ if (!Subtarget.inMips16Mode())
+ FI= MipsFI->initGlobalRegFI();
const TargetRegisterClass *RC = Subtarget.isABI_N64() ?
(const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
@@ -187,6 +190,10 @@
assert(Subtarget.isABI_O32());
+ if (Subtarget.inMips16Mode())
+ return; // no need to load GP. It can be calculated anywhere
+
+
// For O32 ABI, the following instruction sequence is emitted to initialize
// the global base register:
//
Modified: llvm/trunk/test/CodeGen/Mips/null.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/null.ll?rev=158935&r1=158934&r2=158935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/null.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/null.ll Thu Jun 21 15:39:10 2012
@@ -1,9 +1,5 @@
; RUN: llc -march=mipsel -mcpu=mips16 < %s | FileCheck %s -check-prefix=16
-; FIXME: Disabled temporarily because it should not have worked previously
-; and will be fixed after a subsequent patch
-; REQUIRES: disabled
-
define i32 @main() nounwind {
entry:
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