[llvm-commits] [llvm] r158795 - /llvm/trunk/lib/Target/X86/X86InstrSSE.td

[Chris Lattner]

On Jun 20, 2012, at 12:01 AM, Craig Topper wrote:

> Author: ctopper
> Date: Wed Jun 20 02:01:11 2012
> New Revision: 158795
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=158795&view=rev
> Log:
> Add predicate check around some patterns.

Is tblgen not inferring that those Pat patterns require AVX?  If it isn't already, this would be a great enhancement to tblgen that would allow a lot of Pat patterns to be simplified.  It seems that we could infer it from the instructions that feed into the Pat pattern, and potentially even mark register classes (VR256) as requiring the ISA feature.

-Chris

> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86InstrSSE.td
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=158795&r1=158794&r2=158795&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 20 02:01:11 2012
> @@ -4922,10 +4922,12 @@
>                        "cvtpd2dq\t{$src, $dst|$dst, $src}", [],
>                        IIC_SSE_CVT_PD_RR>;
> 
> -def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
> -          (VCVTTPD2DQYrr VR256:$src)>;
> -def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
> -          (VCVTTPD2DQYrm addr:$src)>;
> +let Predicates = [HasAVX] in {
> +  def : Pat<(v4i32 (fp_to_sint (v4f64 VR256:$src))),
> +            (VCVTTPD2DQYrr VR256:$src)>;
> +  def : Pat<(v4i32 (fp_to_sint (memopv4f64 addr:$src))),
> +            (VCVTTPD2DQYrm addr:$src)>;
> +} // Predicates = [HasAVX]
> 
> // Convert Packed DW Integers to Packed Double FP
> let Predicates = [HasAVX] in {
> @@ -4947,20 +4949,22 @@
>                        IIC_SSE_CVT_PD_RM>;
> 
> // AVX 256-bit register conversion intrinsics
> -def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
> -           (VCVTDQ2PDYrr VR128:$src)>;
> -def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
> -           (VCVTDQ2PDYrm addr:$src)>;
> -
> -def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
> -          (VCVTPD2DQYrr VR256:$src)>;
> -def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
> -          (VCVTPD2DQYrm addr:$src)>;
> -
> -def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
> -          (VCVTDQ2PDYrr VR128:$src)>;
> -def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
> -          (VCVTDQ2PDYrm addr:$src)>;
> +let Predicates = [HasAVX] in {
> +  def : Pat<(int_x86_avx_cvtdq2_pd_256 VR128:$src),
> +            (VCVTDQ2PDYrr VR128:$src)>;
> +  def : Pat<(int_x86_avx_cvtdq2_pd_256 (bitconvert (memopv2i64 addr:$src))),
> +            (VCVTDQ2PDYrm addr:$src)>;
> +
> +  def : Pat<(int_x86_avx_cvt_pd2dq_256 VR256:$src),
> +            (VCVTPD2DQYrr VR256:$src)>;
> +  def : Pat<(int_x86_avx_cvt_pd2dq_256 (memopv4f64 addr:$src)),
> +            (VCVTPD2DQYrm addr:$src)>;
> +
> +  def : Pat<(v4f64 (sint_to_fp (v4i32 VR128:$src))),
> +            (VCVTDQ2PDYrr VR128:$src)>;
> +  def : Pat<(v4f64 (sint_to_fp (bc_v4i32 (memopv2i64 addr:$src)))),
> +            (VCVTDQ2PDYrm addr:$src)>;
> +} // Predicates = [HasAVX]
> 
> //===---------------------------------------------------------------------===//
> // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
> 
> 
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