[llvm-commits] [llvm] r158873 - in /llvm/trunk: lib/CodeGen/LiveIntervalAnalysis.cpp test/CodeGen/X86/misched-new.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Wed Jun 20 18:31:34 2012
New Revision: 158873

URL: http://llvm.org/viewvc/llvm-project?rev=158873&view=rev
Log:
Remove the -live-regunits command line option.

Register allocators depend on it being permanently enabled now.

Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/test/CodeGen/X86/misched-new.ll

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=158873&r1=158872&r2=158873&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Wed Jun 20 18:31:34 2012
@@ -27,7 +27,6 @@
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
@@ -40,9 +39,6 @@
 #include <cmath>
 using namespace llvm;
 
-// Temporary option to enable regunit liveness.
-static cl::opt<bool> LiveRegUnits("live-regunits", cl::Hidden, cl::init(true));
-
 STATISTIC(numIntervals , "Number of original intervals");
 
 char LiveIntervals::ID = 0;
@@ -62,8 +58,7 @@
   AU.addRequired<LiveVariables>();
   AU.addPreserved<LiveVariables>();
   AU.addPreservedID(MachineLoopInfoID);
-  if (LiveRegUnits)
-    AU.addRequiredTransitiveID(MachineDominatorsID);
+  AU.addRequiredTransitiveID(MachineDominatorsID);
   AU.addPreservedID(MachineDominatorsID);
   AU.addPreserved<SlotIndexes>();
   AU.addRequiredTransitive<SlotIndexes>();
@@ -109,9 +104,8 @@
   AA = &getAnalysis<AliasAnalysis>();
   LV = &getAnalysis<LiveVariables>();
   Indexes = &getAnalysis<SlotIndexes>();
-  if (LiveRegUnits)
-    DomTree = &getAnalysis<MachineDominatorTree>();
-  if (LiveRegUnits && !LRCalc)
+  DomTree = &getAnalysis<MachineDominatorTree>();
+  if (!LRCalc)
     LRCalc = new LiveRangeCalc();
   AllocatableRegs = TRI->getAllocatableSet(fn);
   ReservedRegs = TRI->getReservedRegs(fn);
@@ -120,9 +114,7 @@
 
   numIntervals += getNumIntervals();
 
-  if (LiveRegUnits) {
-    computeLiveInRegUnits();
-  }
+  computeLiveInRegUnits();
 
   DEBUG(dump());
   return true;

Modified: llvm/trunk/test/CodeGen/X86/misched-new.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/misched-new.ll?rev=158873&r1=158872&r2=158873&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/misched-new.ll (original)
+++ llvm/trunk/test/CodeGen/X86/misched-new.ll Wed Jun 20 18:31:34 2012
@@ -1,5 +1,4 @@
 ; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup < %s
-; RUN: llc -march=x86-64 -mcpu=core2 -enable-misched -misched=shuffle -misched-bottomup -live-regunits < %s
 ; REQUIRES: asserts
 ;
 ; Interesting MachineScheduler cases.