[llvm-commits] [llvm] r158855 - in /llvm/trunk: lib/Target/Mips/Disassembler/MipsDisassembler.cpp lib/Target/Mips/MipsRegisterInfo.td test/MC/Disassembler/Mips/mips32.txt test/MC/Disassembler/Mips/mips32_le.txt test/MC/Disassembler/Mips/mips32r2.txt test/MC/Disassembler/Mips/mips32r2_le.txt
Akira Hatanaka
ahatanaka at mips.com
Wed Jun 20 14:19:39 PDT 2012
Author: ahatanak
Date: Wed Jun 20 16:19:39 2012
New Revision: 158855
URL: http://llvm.org/viewvc/llvm-project?rev=158855&view=rev
Log:
Revert r158846.
Modified:
llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
Modified: llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/Mips/Disassembler/MipsDisassembler.cpp Wed Jun 20 16:19:39 2012
@@ -13,15 +13,16 @@
#include "Mips.h"
#include "MipsSubtarget.h"
-#include "MipsRegisterInfo.h"
#include "llvm/MC/EDInstInfo.h"
#include "llvm/MC/MCDisassembler.h"
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/Support/MathExtras.h"
+
#include "MipsGenEDInfo.inc"
using namespace llvm;
@@ -95,6 +96,58 @@
return instInfoMips;
}
+// Decoder tables for Mips register
+static const uint16_t CPURegsTable[] = {
+ Mips::ZERO, Mips::AT, Mips::V0, Mips::V1,
+ Mips::A0, Mips::A1, Mips::A2, Mips::A3,
+ Mips::T0, Mips::T1, Mips::T2, Mips::T3,
+ Mips::T4, Mips::T5, Mips::T6, Mips::T7,
+ Mips::S0, Mips::S1, Mips::S2, Mips::S3,
+ Mips::S4, Mips::S5, Mips::S6, Mips::S7,
+ Mips::T8, Mips::T9, Mips::K0, Mips::K1,
+ Mips::GP, Mips::SP, Mips::FP, Mips::RA
+};
+
+static const uint16_t FGR32RegsTable[] = {
+ Mips::F0, Mips::F1, Mips::F2, Mips::F3,
+ Mips::F4, Mips::F5, Mips::F6, Mips::F7,
+ Mips::F8, Mips::F9, Mips::F10, Mips::F11,
+ Mips::F12, Mips::F13, Mips::F14, Mips::F15,
+ Mips::F16, Mips::F17, Mips::F18, Mips::F18,
+ Mips::F20, Mips::F21, Mips::F22, Mips::F23,
+ Mips::F24, Mips::F25, Mips::F26, Mips::F27,
+ Mips::F28, Mips::F29, Mips::F30, Mips::F31
+};
+
+static const uint16_t CPU64RegsTable[] = {
+ Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64,
+ Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
+ Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64,
+ Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64,
+ Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64,
+ Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64,
+ Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64,
+ Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64
+};
+
+static const uint16_t FGR64RegsTable[] = {
+ Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64,
+ Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64,
+ Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64,
+ Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
+ Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64,
+ Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64,
+ Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64,
+ Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64
+};
+
+static const uint16_t AFGR64RegsTable[] = {
+ Mips::D0, Mips::D1, Mips::D2, Mips::D3,
+ Mips::D4, Mips::D5, Mips::D6, Mips::D7,
+ Mips::D8, Mips::D9, Mips::D10, Mips::D11,
+ Mips::D12, Mips::D13, Mips::D14, Mips::D15
+};
+
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
static DecodeStatus DecodeCPU64RegsRegisterClass(MCInst &Inst,
@@ -321,7 +374,7 @@
if (RegNo > 31)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPU64RegsRegClass.begin() + RegNo)));
+ Inst.addOperand(MCOperand::CreateReg(CPU64RegsTable[RegNo]));
return MCDisassembler::Success;
}
@@ -331,7 +384,8 @@
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + RegNo)));
+
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo]));
return MCDisassembler::Success;
}
@@ -342,7 +396,7 @@
if (RegNo > 31)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR64RegClass.begin() + RegNo)));
+ Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[RegNo]));
return MCDisassembler::Success;
}
@@ -353,7 +407,7 @@
if (RegNo > 31)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR32RegClass.begin() + RegNo)));
+ Inst.addOperand(MCOperand::CreateReg(FGR32RegsTable[RegNo]));
return MCDisassembler::Success;
}
@@ -374,11 +428,11 @@
int Base = (int)fieldFromInstruction32(Insn, 21, 5);
if(Inst.getOpcode() == Mips::SC){
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Reg)));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
}
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Reg)));
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Base)));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg]));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
@@ -392,8 +446,8 @@
int Reg = (int)fieldFromInstruction32(Insn, 16, 5);
int Base = (int)fieldFromInstruction32(Insn, 21, 5);
- Inst.addOperand(MCOperand::CreateReg(*(Mips::FGR64RegClass.begin() + Reg)));
- Inst.addOperand(MCOperand::CreateReg(*(Mips::CPURegsRegClass.begin() + Base)));
+ Inst.addOperand(MCOperand::CreateReg(FGR64RegsTable[Reg]));
+ Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base]));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
@@ -424,11 +478,10 @@
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
- if (RegNo > 30 || RegNo %2)
+ if (RegNo > 31)
return MCDisassembler::Fail;
- RegNo /=2;
- Inst.addOperand(MCOperand::CreateReg(*(Mips::AFGR64RegClass.begin() + RegNo)));
+ Inst.addOperand(MCOperand::CreateReg(AFGR64RegsTable[RegNo]));
return MCDisassembler::Success;
}
@@ -439,7 +492,7 @@
//Currently only hardware register 29 is supported
if (RegNo != 29)
return MCDisassembler::Fail;
- Inst.addOperand(MCOperand::CreateReg(Mips::HWR29_64));
+ Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
return MCDisassembler::Success;
}
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Wed Jun 20 16:19:39 2012
@@ -70,8 +70,8 @@
let Namespace = "Mips" in {
// General Purpose Registers
- def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
- def AT : MipsGPRReg< 1, "at">, DwarfRegNum<[1]>;
+ def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
+ def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>;
@@ -98,14 +98,14 @@
def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
- def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>;
- def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>;
- def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>;
- def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>;
+ def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
+ def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
+ def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
+ def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
// General Purpose 64-bit Registers
- def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
- def AT_64 : Mips64GPRReg< 1, "at", [AT]>, DwarfRegNum<[1]>;
+ def ZERO_64 : Mips64GPRReg< 0, "ZERO", [ZERO]>, DwarfRegNum<[0]>;
+ def AT_64 : Mips64GPRReg< 1, "AT", [AT]>, DwarfRegNum<[1]>;
def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>;
def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>;
@@ -132,97 +132,97 @@
def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>;
def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>;
def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>;
- def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>;
- def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>;
- def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>;
- def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>;
+ def GP_64 : Mips64GPRReg< 28, "GP", [GP]>, DwarfRegNum<[28]>;
+ def SP_64 : Mips64GPRReg< 29, "SP", [SP]>, DwarfRegNum<[29]>;
+ def FP_64 : Mips64GPRReg< 30, "FP", [FP]>, DwarfRegNum<[30]>;
+ def RA_64 : Mips64GPRReg< 31, "RA", [RA]>, DwarfRegNum<[31]>;
/// Mips Single point precision FPU Registers
- def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
- def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
- def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
- def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
- def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
- def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
- def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
- def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
- def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
- def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
- def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
- def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
- def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
- def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
- def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
- def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
- def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
- def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
- def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
- def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
- def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
- def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
- def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
- def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
- def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
- def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
- def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
- def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
- def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
- def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
- def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
- def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
+ def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>;
+ def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>;
+ def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>;
+ def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>;
+ def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>;
+ def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>;
+ def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>;
+ def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>;
+ def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>;
+ def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>;
+ def F10 : FPR<10, "F10">, DwarfRegNum<[42]>;
+ def F11 : FPR<11, "F11">, DwarfRegNum<[43]>;
+ def F12 : FPR<12, "F12">, DwarfRegNum<[44]>;
+ def F13 : FPR<13, "F13">, DwarfRegNum<[45]>;
+ def F14 : FPR<14, "F14">, DwarfRegNum<[46]>;
+ def F15 : FPR<15, "F15">, DwarfRegNum<[47]>;
+ def F16 : FPR<16, "F16">, DwarfRegNum<[48]>;
+ def F17 : FPR<17, "F17">, DwarfRegNum<[49]>;
+ def F18 : FPR<18, "F18">, DwarfRegNum<[50]>;
+ def F19 : FPR<19, "F19">, DwarfRegNum<[51]>;
+ def F20 : FPR<20, "F20">, DwarfRegNum<[52]>;
+ def F21 : FPR<21, "F21">, DwarfRegNum<[53]>;
+ def F22 : FPR<22, "F22">, DwarfRegNum<[54]>;
+ def F23 : FPR<23, "F23">, DwarfRegNum<[55]>;
+ def F24 : FPR<24, "F24">, DwarfRegNum<[56]>;
+ def F25 : FPR<25, "F25">, DwarfRegNum<[57]>;
+ def F26 : FPR<26, "F26">, DwarfRegNum<[58]>;
+ def F27 : FPR<27, "F27">, DwarfRegNum<[59]>;
+ def F28 : FPR<28, "F28">, DwarfRegNum<[60]>;
+ def F29 : FPR<29, "F29">, DwarfRegNum<[61]>;
+ def F30 : FPR<30, "F30">, DwarfRegNum<[62]>;
+ def F31 : FPR<31, "F31">, DwarfRegNum<[63]>;
/// Mips Double point precision FPU Registers (aliased
/// with the single precision to hold 64 bit values)
- def D0 : AFPR< 0, "f0", [F0, F1]>;
- def D1 : AFPR< 2, "f2", [F2, F3]>;
- def D2 : AFPR< 4, "f4", [F4, F5]>;
- def D3 : AFPR< 6, "f6", [F6, F7]>;
- def D4 : AFPR< 8, "f8", [F8, F9]>;
- def D5 : AFPR<10, "f10", [F10, F11]>;
- def D6 : AFPR<12, "f12", [F12, F13]>;
- def D7 : AFPR<14, "f14", [F14, F15]>;
- def D8 : AFPR<16, "f16", [F16, F17]>;
- def D9 : AFPR<18, "f18", [F18, F19]>;
- def D10 : AFPR<20, "f20", [F20, F21]>;
- def D11 : AFPR<22, "f22", [F22, F23]>;
- def D12 : AFPR<24, "f24", [F24, F25]>;
- def D13 : AFPR<26, "f26", [F26, F27]>;
- def D14 : AFPR<28, "f28", [F28, F29]>;
- def D15 : AFPR<30, "f30", [F30, F31]>;
+ def D0 : AFPR< 0, "F0", [F0, F1]>;
+ def D1 : AFPR< 2, "F2", [F2, F3]>;
+ def D2 : AFPR< 4, "F4", [F4, F5]>;
+ def D3 : AFPR< 6, "F6", [F6, F7]>;
+ def D4 : AFPR< 8, "F8", [F8, F9]>;
+ def D5 : AFPR<10, "F10", [F10, F11]>;
+ def D6 : AFPR<12, "F12", [F12, F13]>;
+ def D7 : AFPR<14, "F14", [F14, F15]>;
+ def D8 : AFPR<16, "F16", [F16, F17]>;
+ def D9 : AFPR<18, "F18", [F18, F19]>;
+ def D10 : AFPR<20, "F20", [F20, F21]>;
+ def D11 : AFPR<22, "F22", [F22, F23]>;
+ def D12 : AFPR<24, "F24", [F24, F25]>;
+ def D13 : AFPR<26, "F26", [F26, F27]>;
+ def D14 : AFPR<28, "F28", [F28, F29]>;
+ def D15 : AFPR<30, "F30", [F30, F31]>;
/// Mips Double point precision FPU Registers in MFP64 mode.
- def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>;
- def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>;
- def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>;
- def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>;
- def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>;
- def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>;
- def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>;
- def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>;
- def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>;
- def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>;
- def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>;
- def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>;
- def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>;
- def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>;
- def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>;
- def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>;
- def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>;
- def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>;
- def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>;
- def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>;
- def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>;
- def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>;
- def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>;
- def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>;
- def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>;
- def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>;
- def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>;
- def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>;
- def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>;
- def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>;
- def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>;
- def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>;
+ def D0_64 : AFPR64<0, "F0", [F0]>, DwarfRegNum<[32]>;
+ def D1_64 : AFPR64<1, "F1", [F1]>, DwarfRegNum<[33]>;
+ def D2_64 : AFPR64<2, "F2", [F2]>, DwarfRegNum<[34]>;
+ def D3_64 : AFPR64<3, "F3", [F3]>, DwarfRegNum<[35]>;
+ def D4_64 : AFPR64<4, "F4", [F4]>, DwarfRegNum<[36]>;
+ def D5_64 : AFPR64<5, "F5", [F5]>, DwarfRegNum<[37]>;
+ def D6_64 : AFPR64<6, "F6", [F6]>, DwarfRegNum<[38]>;
+ def D7_64 : AFPR64<7, "F7", [F7]>, DwarfRegNum<[39]>;
+ def D8_64 : AFPR64<8, "F8", [F8]>, DwarfRegNum<[40]>;
+ def D9_64 : AFPR64<9, "F9", [F9]>, DwarfRegNum<[41]>;
+ def D10_64 : AFPR64<10, "F10", [F10]>, DwarfRegNum<[42]>;
+ def D11_64 : AFPR64<11, "F11", [F11]>, DwarfRegNum<[43]>;
+ def D12_64 : AFPR64<12, "F12", [F12]>, DwarfRegNum<[44]>;
+ def D13_64 : AFPR64<13, "F13", [F13]>, DwarfRegNum<[45]>;
+ def D14_64 : AFPR64<14, "F14", [F14]>, DwarfRegNum<[46]>;
+ def D15_64 : AFPR64<15, "F15", [F15]>, DwarfRegNum<[47]>;
+ def D16_64 : AFPR64<16, "F16", [F16]>, DwarfRegNum<[48]>;
+ def D17_64 : AFPR64<17, "F17", [F17]>, DwarfRegNum<[49]>;
+ def D18_64 : AFPR64<18, "F18", [F18]>, DwarfRegNum<[50]>;
+ def D19_64 : AFPR64<19, "F19", [F19]>, DwarfRegNum<[51]>;
+ def D20_64 : AFPR64<20, "F20", [F20]>, DwarfRegNum<[52]>;
+ def D21_64 : AFPR64<21, "F21", [F21]>, DwarfRegNum<[53]>;
+ def D22_64 : AFPR64<22, "F22", [F22]>, DwarfRegNum<[54]>;
+ def D23_64 : AFPR64<23, "F23", [F23]>, DwarfRegNum<[55]>;
+ def D24_64 : AFPR64<24, "F24", [F24]>, DwarfRegNum<[56]>;
+ def D25_64 : AFPR64<25, "F25", [F25]>, DwarfRegNum<[57]>;
+ def D26_64 : AFPR64<26, "F26", [F26]>, DwarfRegNum<[58]>;
+ def D27_64 : AFPR64<27, "F27", [F27]>, DwarfRegNum<[59]>;
+ def D28_64 : AFPR64<28, "F28", [F28]>, DwarfRegNum<[60]>;
+ def D29_64 : AFPR64<29, "F29", [F29]>, DwarfRegNum<[61]>;
+ def D30_64 : AFPR64<30, "F30", [F30]>, DwarfRegNum<[62]>;
+ def D31_64 : AFPR64<31, "F31", [F31]>, DwarfRegNum<[63]>;
// Hi/Lo registers
def HI : Register<"hi">, DwarfRegNum<[64]>;
@@ -236,9 +236,6 @@
// Status flags register
def FCR31 : Register<"31">;
- // fcc0 register
- def FCC0 : Register<"fcc0">;
-
// Hardware register $29
def HWR29 : Register<"29">;
def HWR29_64 : Register<"29">;
@@ -249,32 +246,24 @@
//===----------------------------------------------------------------------===//
def CPURegs : RegisterClass<"Mips", [i32], 32, (add
- // Reserved
- ZERO, AT,
// Return Values and Arguments
V0, V1, A0, A1, A2, A3,
// Not preserved across procedure calls
- T0, T1, T2, T3, T4, T5, T6, T7,
+ T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
// Callee save
S0, S1, S2, S3, S4, S5, S6, S7,
- // Not preserved across procedure calls
- T8, T9,
// Reserved
- K0, K1, GP, SP, FP, RA)>;
+ ZERO, AT, K0, K1, GP, SP, FP, RA)>;
def CPU64Regs : RegisterClass<"Mips", [i64], 64, (add
-// Reserved
- ZERO_64, AT_64,
// Return Values and Arguments
V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
// Not preserved across procedure calls
- T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
+ T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, T8_64, T9_64,
// Callee save
S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
- // Not preserved across procedure calls
- T8_64, T9_64,
// Reserved
- K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
+ ZERO_64, AT_64, K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
// Return Values and Arguments
@@ -296,20 +285,16 @@
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments
- D0, D1,
- // Not preserved across procedure calls
- D2, D3, D4, D5,
- // Return Values and Arguments
- D6, D7,
+ D0, D1, D6, D7,
// Not preserved across procedure calls
- D8, D9,
+ D2, D3, D4, D5, D8, D9,
// Callee save
D10, D11, D12, D13, D14, D15)>;
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
// Condition Register for floating point operations
-def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>;
+def CCR : RegisterClass<"Mips", [i32], 32, (add FCR31)>;
// Hi/Lo Registers
def HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>;
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32.txt?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32.txt Wed Jun 20 16:19:39 2012
@@ -1,7 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux
# CHECK: abs.d $f12,$f14
-0x46 0x20 0x73 0x05
+0x46 0x20 0x39 0x85
# CHECK: abs.s $f6,$f7
0x46 0x00 0x39 0x85
@@ -9,8 +9,8 @@
# CHECK: add t1,a2,a3
0x00 0xc7 0x48 0x20
-# CHECK: add.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x00
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
# CHECK: add.s $f9,$f6,$f7
0x46 0x07 0x32 0x40
@@ -61,103 +61,103 @@
0x15 0x26 0x01 0x4c
# CHECK: c.eq.d $f12,$f14
-0x46 0x2e 0x60 0x32
+0x46 0x27 0x30 0x32
# CHECK: c.eq.s $f6,$f7
0x46 0x07 0x30 0x32
# CHECK: c.f.d $f12,$f14
-0x46 0x2e 0x60 0x30
+0x46 0x27 0x30 0x30
# CHECK: c.f.s $f6,$f7
0x46 0x07 0x30 0x30
# CHECK: c.le.d $f12,$f14
-0x46 0x2e 0x60 0x3e
+0x46 0x27 0x30 0x3e
# CHECK: c.le.s $f6,$f7
0x46 0x07 0x30 0x3e
# CHECK: c.lt.d $f12,$f14
-0x46 0x2e 0x60 0x3c
+0x46 0x27 0x30 0x3c
# CHECK: c.lt.s $f6,$f7
0x46 0x07 0x30 0x3c
# CHECK: c.nge.d $f12,$f14
-0x46 0x2e 0x60 0x3d
+0x46 0x27 0x30 0x3d
# CHECK: c.nge.s $f6,$f7
0x46 0x07 0x30 0x3d
# CHECK: c.ngl.d $f12,$f14
-0x46 0x2e 0x60 0x3b
+0x46 0x27 0x30 0x3b
# CHECK: c.ngl.s $f6,$f7
0x46 0x07 0x30 0x3b
# CHECK: c.ngle.d $f12,$f14
-0x46 0x2e 0x60 0x39
+0x46 0x27 0x30 0x39
# CHECK: c.ngle.s $f6,$f7
0x46 0x07 0x30 0x39
# CHECK: c.ngt.d $f12,$f14
-0x46 0x2e 0x60 0x3f
+0x46 0x27 0x30 0x3f
# CHECK: c.ngt.s $f6,$f7
0x46 0x07 0x30 0x3f
# CHECK: c.ole.d $f12,$f14
-0x46 0x2e 0x60 0x36
+0x46 0x27 0x30 0x36
# CHECK: c.ole.s $f6,$f7
0x46 0x07 0x30 0x36
# CHECK: c.olt.d $f12,$f14
-0x46 0x2e 0x60 0x34
+0x46 0x27 0x30 0x34
# CHECK: c.olt.s $f6,$f7
0x46 0x07 0x30 0x34
# CHECK: c.seq.d $f12,$f14
-0x46 0x2e 0x60 0x3a
+0x46 0x27 0x30 0x3a
# CHECK: c.seq.s $f6,$f7
0x46 0x07 0x30 0x3a
# CHECK: c.sf.d $f12,$f14
-0x46 0x2e 0x60 0x38
+0x46 0x27 0x30 0x38
# CHECK: c.sf.s $f6,$f7
0x46 0x07 0x30 0x38
# CHECK: c.ueq.d $f12,$f14
-0x46 0x2e 0x60 0x33
+0x46 0x27 0x30 0x33
# CHECK: c.ueq.s $f28,$f18
0x46 0x12 0xe0 0x33
# CHECK: c.ule.d $f12,$f14
-0x46 0x2e 0x60 0x37
+0x46 0x27 0x30 0x37
# CHECK: c.ule.s $f6,$f7
0x46 0x07 0x30 0x37
# CHECK: c.ult.d $f12,$f14
-0x46 0x2e 0x60 0x35
+0x46 0x27 0x30 0x35
# CHECK: c.ult.s $f6,$f7
0x46 0x07 0x30 0x35
# CHECK: c.un.d $f12,$f14
-0x46 0x2e 0x60 0x31
+0x46 0x27 0x30 0x31
# CHECK: c.un.s $f6,$f7
0x46 0x07 0x30 0x31
# CHECK: ceil.w.d $f12,$f14
-0x46 0x20 0x73 0x0e
+0x46 0x20 0x39 0x8e
# CHECK: ceil.w.s $f6,$f7
0x46 0x00 0x39 0x8e
@@ -175,25 +175,31 @@
0x44 0xc6 0x38 0x00
# CHECK: cvt.d.s $f6,$f7
-0x46 0x00 0x39 0xa1
+0x46 0x00 0x38 0xa1
# CHECK: cvt.d.w $f12,$f14
-0x46 0x80 0x73 0x21
+0x46 0x80 0x38 0xa1
+
+# CHECK: cvt.l.d $f12,$f14
+0x46 0x20 0x39 0xa5
+
+# CHECK: cvt.l.s $f6,$f7
+0x46 0x00 0x39 0xa5
# CHECK: cvt.s.d $f12,$f14
-0x46 0x20 0x73 0x20
+0x46 0x20 0x39 0xa0
# CHECK: cvt.s.w $f6,$f7
0x46 0x80 0x39 0xa0
# CHECK: cvt.w.d $f12,$f14
-0x46 0x20 0x73 0x24
+0x46 0x20 0x39 0xa4
# CHECK: cvt.w.s $f6,$f7
0x46 0x00 0x39 0xa4
# CHECK: floor.w.d $f12,$f14
-0x46 0x20 0x73 0x0f
+0x46 0x20 0x39 0x8f
# CHECK: floor.w.s $f6,$f7
0x46 0x00 0x39 0x8f
@@ -240,12 +246,6 @@
# CHECK: lwc1 $f9,9158(a3)
0xc4 0xe9 0x23 0xc6
-# CHECK: lwl $v0, 3($a0)
-0x88 0x82 0x00 0x03
-
-# CHECK: lwr $v1,16($a1)
-0x98 0xa3 0x00 0x10
-
# CHECK: madd a2,a3
0x70 0xc7 0x00 0x00
@@ -261,8 +261,8 @@
# CHECK: mflo a1
0x00 0x00 0x28 0x12
-# CHECK: mov.d $f6,$f8
-0x46 0x20 0x41 0x86
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
# CHECK: mov.s $f6,$f7
0x46 0x00 0x39 0x86
@@ -285,8 +285,8 @@
# CHECK: mtlo a3
0x00 0xe0 0x00 0x13
-# CHECK: mul.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x02
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
# CHECK: mul.s $f9,$f6,$f7
0x46 0x07 0x32 0x42
@@ -301,7 +301,7 @@
0x00 0x65 0x00 0x19
# CHECK: neg.d $f12,$f14
-0x46 0x20 0x73 0x07
+0x46 0x20 0x39 0x87
# CHECK: neg.s $f6,$f7
0x46 0x00 0x39 0x87
@@ -327,8 +327,8 @@
# CHECK: rdhwr a2,$29
0x7c 0x06 0xe8 0x3b
-# CHECK: round.w.d $f6,$f14
-0x46 0x20 0x73 0x0c
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
# CHECK: round.w.s $f6,$f7
0x46 0x00 0x39 0x8c
@@ -367,7 +367,7 @@
0x00 0x65 0x18 0x2b
# CHECK: sqrt.d $f12,$f14
-0x46 0x20 0x73 0x04
+0x46 0x20 0x39 0x84
# CHECK: sqrt.s $f6,$f7
0x46 0x00 0x39 0x84
@@ -387,8 +387,8 @@
# CHECK: srlv v0,v1,a1
0x00 0xa3 0x10 0x06
-# CHECK: sub.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x01
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
# CHECK: sub.s $f9,$f6,$f7
0x46 0x07 0x32 0x41
@@ -405,17 +405,11 @@
# CHECK: swc1 $f9,9158(a3)
0xe4 0xe9 0x23 0xc6
-# CHECK: swl $a0, 16($a1)
-0xa8 0xa4 0x00 0x10
-
-# CHECK: swr $a2, 16($a3)
-0xb8 0xe6 0x00 0x10
-
# CHECK: sync 0x7
0x00 0x00 0x01 0xcf
# CHECK: trunc.w.d $f12,$f14
-0x46 0x20 0x73 0x0d
+0x46 0x20 0x39 0x8d
# CHECK: trunc.w.s $f6,$f7
0x46 0x00 0x39 0x8d
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt Wed Jun 20 16:19:39 2012
@@ -1,7 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux
# CHECK: abs.d $f12,$f14
-0x05 0x73 0x20 0x46
+0x85 0x39 0x20 0x46
# CHECK: abs.s $f6,$f7
0x85 0x39 0x00 0x46
@@ -9,8 +9,8 @@
# CHECK: add t1,a2,a3
0x20 0x48 0xc7 0x00
-# CHECK: add.d $8,$f12,$f14
-0x00 0x62 0x2e 0x46
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
# CHECK: add.s $f9,$f6,$f7
0x40 0x32 0x07 0x46
@@ -61,106 +61,106 @@
0x4c 0x01 0x26 0x15
# CHECK: c.eq.d $f12,$f14
-0x32 0x60 0x2e 0x46
+0x32 0x30 0x27 0x46
# CHECK: c.eq.s $f6,$f7
0x32 0x30 0x07 0x46
# CHECK: c.f.d $f12,$f14
-0x30 0x60 0x2e 0x46
+0x30 0x30 0x27 0x46
# CHECK: c.f.s $f6,$f7
0x30 0x30 0x07 0x46
# CHECK: c.le.d $f12,$f14
-0x3e 0x60 0x2e 0x46
+0x3e 0x30 0x27 0x46
# CHECK: c.le.s $f6,$f7
0x3e 0x30 0x07 0x46
# CHECK: c.lt.d $f12,$f14
-0x3c 0x60 0x2e 0x46
+0x3c 0x30 0x27 0x46
# CHECK: c.lt.s $f6,$f7
0x3c 0x30 0x07 0x46
# CHECK: c.nge.d $f12,$f14
-0x3d 0x60 0x2e 0x46
+0x3d 0x30 0x27 0x46
# CHECK: c.nge.s $f6,$f7
0x3d 0x30 0x07 0x46
# CHECK: c.ngl.d $f12,$f14
-0x3b 0x60 0x2e 0x46
+0x3b 0x30 0x27 0x46
# CHECK: c.ngl.s $f6,$f7
0x3b 0x30 0x07 0x46
# CHECK: c.ngle.d $f12,$f14
-0x39 0x60 0x2e 0x46
+0x39 0x30 0x27 0x46
# CHECK: c.ngle.s $f6,$f7
0x39 0x30 0x07 0x46
# CHECK: c.ngt.d $f12,$f14
-0x3f 0x60 0x2e 0x46
+0x3f 0x30 0x27 0x46
# CHECK: c.ngt.s $f6,$f7
0x3f 0x30 0x07 0x46
# CHECK: c.ole.d $f12,$f14
-0x36 0x60 0x2e 0x46
+0x36 0x30 0x27 0x46
# CHECK: c.ole.s $f6,$f7
0x36 0x30 0x07 0x46
# CHECK: c.olt.d $f12,$f14
-0x34 0x60 0x2e 0x46
+0x34 0x30 0x27 0x46
# CHECK: c.olt.s $f6,$f7
0x34 0x30 0x07 0x46
# CHECK: c.seq.d $f12,$f14
-0x3a 0x60 0x2e 0x46
+0x3a 0x30 0x27 0x46
# CHECK: c.seq.s $f6,$f7
0x3a 0x30 0x07 0x46
# CHECK: c.sf.d $f12,$f14
-0x38 0x60 0x2e 0x46
+0x38 0x30 0x27 0x46
# CHECK: c.sf.s $f6,$f7
0x38 0x30 0x07 0x46
# CHECK: c.ueq.d $f12,$f14
-0x33 0x60 0x2e 0x46
+0x33 0x30 0x27 0x46
# CHECK: c.ueq.s $f28,$f18
0x33 0xe0 0x12 0x46
# CHECK: c.ule.d $f12,$f14
-0x37 0x60 0x2e 0x46
+0x37 0x30 0x27 0x46
# CHECK: c.ule.s $f6,$f7
0x37 0x30 0x07 0x46
# CHECK: c.ult.d $f12,$f14
-0x35 0x60 0x2e 0x46
+0x35 0x30 0x27 0x46
# CHECK: c.ult.s $f6,$f7
0x35 0x30 0x07 0x46
# CHECK: c.un.d $f12,$f14
-0x31 0x60 0x2e 0x46
+0x31 0x30 0x27 0x46
# CHECK: c.un.s $f6,$f7
0x31 0x30 0x07 0x46
# CHECK: ceil.w.d $f12,$f14
-0x0e 0x73 0x20 0x46
+0x8e 0x38 0x20 0x46
# CHECK: ceil.w.s $f6,$f7
-0x0e 0x73 0x20 0x46
+0x8e 0x38 0x00 0x46
# CHECK: cfc1 a2,$7
0x00 0x38 0x46 0x44
@@ -178,22 +178,28 @@
0xa1 0x39 0x00 0x46
# CHECK: cvt.d.w $f12,$f14
-0x21 0x73 0x80 0x46
+0xa1 0x39 0x80 0x46
+
+# CHECK: cvt.l.d $f12,$f14
+0xa5 0x39 0x20 0x46
+
+# CHECK: cvt.l.s $f6,$f7
+0xa5 0x39 0x00 0x46
# CHECK: cvt.s.d $f12,$f14
-0x20 0x73 0x20 0x46
+0xa0 0x39 0x20 0x46
# CHECK: cvt.s.w $f6,$f7
0xa0 0x39 0x80 0x46
# CHECK: cvt.w.d $f12,$f14
-0x24 0x73 0x20 0x46
+0xa4 0x39 0x20 0x46
# CHECK: cvt.w.s $f6,$f7
0xa4 0x39 0x00 0x46
# CHECK: floor.w.d $f12,$f14
-0x0f 0x73 0x20 0x46
+0x8f 0x39 0x20 0x46
# CHECK: floor.w.s $f6,$f7
0x8f 0x39 0x00 0x46
@@ -204,7 +210,7 @@
# CHECK: jal 00000530
0x4c 0x01 0x00 0x0c
-# CHECK: jalr a3
+# CHECK: jalr a2,a3
0x09 0xf8 0xe0 0x00
# CHECK: jr a3
@@ -243,12 +249,6 @@
# CHECK: lwc1 $f9,9158(a3)
0xc6 0x23 0xe9 0xc4
-# CHECK: lwl $v0, 3($a0)
-0x03 0x00 0x82 0x88
-
-# CHECK: lwr $v1,16($a1)
-0x10 0x00 0xa3 0x98
-
# CHECK: madd a2,a3
0x00 0x00 0xc7 0x70
@@ -264,8 +264,8 @@
# CHECK: mflo a1
0x12 0x28 0x00 0x00
-# CHECK: mov.d $f6,$f8
-0x86 0x41 0x20 0x46
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
# CHECK: mov.s $f6,$f7
0x86 0x39 0x00 0x46
@@ -288,11 +288,11 @@
# CHECK: mtlo a3
0x13 0x00 0xe0 0x00
-# CHECK: mul.d $f8,$f12,$f14
-0x02 0x62 0x2e 0x46
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
# CHECK: mul.s $f9,$f6,$f7
-0x02 0x62 0x07 0x46
+0x42 0x32 0x07 0x46
# CHECK: mul t1,a2,a3
0x02 0x48 0xc7 0x70
@@ -304,7 +304,7 @@
0x19 0x00 0x65 0x00
# CHECK: neg.d $f12,$f14
-0x07 0x73 0x20 0x46
+0x87 0x39 0x20 0x46
# CHECK: neg.s $f6,$f7
0x87 0x39 0x00 0x46
@@ -331,7 +331,7 @@
0x3b 0xe8 0x06 0x7c
# CHECK: round.w.d $f12,$f14
-0x0c 0x73 0x20 0x46
+0x8c 0x39 0x20 0x46
# CHECK: round.w.s $f6,$f7
0x8c 0x39 0x00 0x46
@@ -370,7 +370,7 @@
0x2b 0x18 0x65 0x00
# CHECK: sqrt.d $f12,$f14
-0x04 0x73 0x20 0x46
+0x84 0x39 0x20 0x46
# CHECK: sqrt.s $f6,$f7
0x84 0x39 0x00 0x46
@@ -390,8 +390,8 @@
# CHECK: srlv v0,v1,a1
0x06 0x10 0xa3 0x00
-# CHECK: sub.d $f8,$f12,$f14
-0x01 0x62 0x2e 0x46
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
# CHECK: sub.s $f9,$f6,$f7
0x41 0x32 0x07 0x46
@@ -408,17 +408,11 @@
# CHECK: swc1 $f9,9158(a3)
0xc6 0x23 0xe9 0xe4
-# CHECK: swl $a0, 16($a1)
-0x10 0x00 0xa4 0xa8
-
-# CHECK: swr $a2, 16($a3)
-0x10 0x00 0xe6 0xb8
-
# CHECK: sync 0x7
0xcf 0x01 0x00 0x00
# CHECK: trunc.w.d $f12,$f14
-0x0d 0x73 0x20 0x46
+0x8d 0x39 0x20 0x46
# CHECK: trunc.w.s $f6,$f7
0x8d 0x39 0x00 0x46
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2.txt Wed Jun 20 16:19:39 2012
@@ -1,7 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r2
# CHECK: abs.d $f12,$f14
-0x46 0x20 0x73 0x05
+0x46 0x20 0x39 0x85
# CHECK: abs.s $f6,$f7
0x46 0x00 0x39 0x85
@@ -9,8 +9,8 @@
# CHECK: add t1,a2,a3
0x00 0xc7 0x48 0x20
-# CHECK: add.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x00
+# CHECK: add.d $f18,$f12,$f14
+0x46 0x27 0x32 0x40
# CHECK: add.s $f9,$f6,$f7
0x46 0x07 0x32 0x40
@@ -61,103 +61,103 @@
0x15 0x26 0x01 0x4c
# CHECK: c.eq.d $f12,$f14
-0x46 0x2e 0x60 0x32
+0x46 0x27 0x30 0x32
# CHECK: c.eq.s $f6,$f7
0x46 0x07 0x30 0x32
# CHECK: c.f.d $f12,$f14
-0x46 0x2e 0x60 0x30
+0x46 0x27 0x30 0x30
# CHECK: c.f.s $f6,$f7
0x46 0x07 0x30 0x30
# CHECK: c.le.d $f12,$f14
-0x46 0x2e 0x60 0x3e
+0x46 0x27 0x30 0x3e
# CHECK: c.le.s $f6,$f7
0x46 0x07 0x30 0x3e
# CHECK: c.lt.d $f12,$f14
-0x46 0x2e 0x60 0x3c
+0x46 0x27 0x30 0x3c
# CHECK: c.lt.s $f6,$f7
0x46 0x07 0x30 0x3c
# CHECK: c.nge.d $f12,$f14
-0x46 0x2e 0x60 0x3d
+0x46 0x27 0x30 0x3d
# CHECK: c.nge.s $f6,$f7
0x46 0x07 0x30 0x3d
# CHECK: c.ngl.d $f12,$f14
-0x46 0x2e 0x60 0x3b
+0x46 0x27 0x30 0x3b
# CHECK: c.ngl.s $f6,$f7
0x46 0x07 0x30 0x3b
# CHECK: c.ngle.d $f12,$f14
-0x46 0x2e 0x60 0x39
+0x46 0x27 0x30 0x39
# CHECK: c.ngle.s $f6,$f7
0x46 0x07 0x30 0x39
# CHECK: c.ngt.d $f12,$f14
-0x46 0x2e 0x60 0x3f
+0x46 0x27 0x30 0x3f
# CHECK: c.ngt.s $f6,$f7
0x46 0x07 0x30 0x3f
# CHECK: c.ole.d $f12,$f14
-0x46 0x2e 0x60 0x36
+0x46 0x27 0x30 0x36
# CHECK: c.ole.s $f6,$f7
0x46 0x07 0x30 0x36
# CHECK: c.olt.d $f12,$f14
-0x46 0x2e 0x60 0x34
+0x46 0x27 0x30 0x34
# CHECK: c.olt.s $f6,$f7
0x46 0x07 0x30 0x34
# CHECK: c.seq.d $f12,$f14
-0x46 0x2e 0x60 0x3a
+0x46 0x27 0x30 0x3a
# CHECK: c.seq.s $f6,$f7
0x46 0x07 0x30 0x3a
# CHECK: c.sf.d $f12,$f14
-0x46 0x2e 0x60 0x38
+0x46 0x27 0x30 0x38
# CHECK: c.sf.s $f6,$f7
0x46 0x07 0x30 0x38
# CHECK: c.ueq.d $f12,$f14
-0x46 0x2e 0x60 0x33
+0x46 0x27 0x30 0x33
# CHECK: c.ueq.s $f28,$f18
0x46 0x12 0xe0 0x33
# CHECK: c.ule.d $f12,$f14
-0x46 0x2e 0x60 0x37
+0x46 0x27 0x30 0x37
# CHECK: c.ule.s $f6,$f7
0x46 0x07 0x30 0x37
# CHECK: c.ult.d $f12,$f14
-0x46 0x2e 0x60 0x35
+0x46 0x27 0x30 0x35
# CHECK: c.ult.s $f6,$f7
0x46 0x07 0x30 0x35
# CHECK: c.un.d $f12,$f14
-0x46 0x2e 0x60 0x31
+0x46 0x27 0x30 0x31
# CHECK: c.un.s $f6,$f7
0x46 0x07 0x30 0x31
# CHECK: ceil.w.d $f12,$f14
-0x46 0x20 0x73 0x0e
+0x46 0x20 0x39 0x8e
# CHECK: ceil.w.s $f6,$f7
0x46 0x00 0x39 0x8e
@@ -175,31 +175,31 @@
0x44 0xc6 0x38 0x00
# CHECK: cvt.d.s $f6,$f7
-0x46 0x00 0x39 0xa1
+0x46 0x00 0x38 0xa1
# CHECK: cvt.d.w $f12,$f14
-0x46 0x80 0x73 0x21
+0x46 0x80 0x38 0xa1
# CHECK: cvt.l.d $f12,$f14
-0x46 0x20 0x73 0x05
+0x46 0x20 0x39 0xa5
# CHECK: cvt.l.s $f6,$f7
0x46 0x00 0x39 0xa5
# CHECK: cvt.s.d $f12,$f14
-0x46 0x20 0x73 0x20
+0x46 0x20 0x39 0xa0
# CHECK: cvt.s.w $f6,$f7
0x46 0x80 0x39 0xa0
# CHECK: cvt.w.d $f12,$f14
-0x46 0x20 0x73 0x24
+0x46 0x20 0x39 0xa4
# CHECK: cvt.w.s $f6,$f7
0x46 0x00 0x39 0xa4
# CHECK: floor.w.d $f12,$f14
-0x46 0x20 0x73 0x0f
+0x46 0x20 0x39 0x8f
# CHECK: floor.w.s $f6,$f7
0x46 0x00 0x39 0x8f
@@ -264,8 +264,8 @@
# CHECK: mflo a1
0x00 0x00 0x28 0x12
-# CHECK: mov.d $f6,$f8
-0x46 0x20 0x41 0x86
+# CHECK: mov.d $f6,$f7
+0x46 0x20 0x39 0x86
# CHECK: mov.s $f6,$f7
0x46 0x00 0x39 0x86
@@ -288,8 +288,8 @@
# CHECK: mtlo a3
0x00 0xe0 0x00 0x13
-# CHECK: mul.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x02
+# CHECK: mul.d $f9,$f12,$f14
+0x46 0x27 0x32 0x42
# CHECK: mul.s $f9,$f6,$f7
0x46 0x07 0x32 0x42
@@ -304,7 +304,7 @@
0x00 0x65 0x00 0x19
# CHECK: neg.d $f12,$f14
-0x46 0x20 0x73 0x07
+0x46 0x20 0x39 0x87
# CHECK: neg.s $f6,$f7
0x46 0x00 0x39 0x87
@@ -336,8 +336,8 @@
# CHECK: rorv t1,a2,a3
0x00 0xe6 0x48 0x46
-# CHECK: round.w.d $f6,$f14
-0x46 0x20 0x73 0x0c
+# CHECK: round.w.d $f12,$f14
+0x46 0x20 0x39 0x8c
# CHECK: round.w.s $f6,$f7
0x46 0x00 0x39 0x8c
@@ -382,7 +382,7 @@
0x00 0x65 0x18 0x2b
# CHECK: sqrt.d $f12,$f14
-0x46 0x20 0x73 0x04
+0x46 0x20 0x39 0x84
# CHECK: sqrt.s $f6,$f7
0x46 0x00 0x39 0x84
@@ -402,8 +402,8 @@
# CHECK: srlv v0,v1,a1
0x00 0xa3 0x10 0x06
-# CHECK: sub.d $f8,$f12,$f14
-0x46 0x2e 0x62 0x01
+# CHECK: sub.d $f9,$f12,$f14
+0x46 0x27 0x32 0x41
# CHECK: sub.s $f9,$f6,$f7
0x46 0x07 0x32 0x41
@@ -424,7 +424,7 @@
0x00 0x00 0x01 0xcf
# CHECK: trunc.w.d $f12,$f14
-0x46 0x20 0x73 0x0d
+0x46 0x20 0x39 0x8d
# CHECK: trunc.w.s $f6,$f7
0x46 0x00 0x39 0x8d
Modified: llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt?rev=158855&r1=158854&r2=158855&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2_le.txt Wed Jun 20 16:19:39 2012
@@ -1,7 +1,7 @@
# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mcpu=mips32r2
# CHECK: abs.d $f12,$f14
-0x05 0x73 0x20 0x46
+0x85 0x39 0x20 0x46
# CHECK: abs.s $f6,$f7
0x85 0x39 0x00 0x46
@@ -9,8 +9,8 @@
# CHECK: add t1,a2,a3
0x20 0x48 0xc7 0x00
-# CHECK: add.d $8,$f12,$f14
-0x00 0x62 0x2e 0x46
+# CHECK: add.d $f18,$f12,$f14
+0x40 0x32 0x27 0x46
# CHECK: add.s $f9,$f6,$f7
0x40 0x32 0x07 0x46
@@ -61,106 +61,106 @@
0x4c 0x01 0x26 0x15
# CHECK: c.eq.d $f12,$f14
-0x32 0x60 0x2e 0x46
+0x32 0x30 0x27 0x46
# CHECK: c.eq.s $f6,$f7
0x32 0x30 0x07 0x46
# CHECK: c.f.d $f12,$f14
-0x30 0x60 0x2e 0x46
+0x30 0x30 0x27 0x46
# CHECK: c.f.s $f6,$f7
0x30 0x30 0x07 0x46
# CHECK: c.le.d $f12,$f14
-0x3e 0x60 0x2e 0x46
+0x3e 0x30 0x27 0x46
# CHECK: c.le.s $f6,$f7
0x3e 0x30 0x07 0x46
# CHECK: c.lt.d $f12,$f14
-0x3c 0x60 0x2e 0x46
+0x3c 0x30 0x27 0x46
# CHECK: c.lt.s $f6,$f7
0x3c 0x30 0x07 0x46
# CHECK: c.nge.d $f12,$f14
-0x3d 0x60 0x2e 0x46
+0x3d 0x30 0x27 0x46
# CHECK: c.nge.s $f6,$f7
0x3d 0x30 0x07 0x46
# CHECK: c.ngl.d $f12,$f14
-0x3b 0x60 0x2e 0x46
+0x3b 0x30 0x27 0x46
# CHECK: c.ngl.s $f6,$f7
0x3b 0x30 0x07 0x46
# CHECK: c.ngle.d $f12,$f14
-0x39 0x60 0x2e 0x46
+0x39 0x30 0x27 0x46
# CHECK: c.ngle.s $f6,$f7
0x39 0x30 0x07 0x46
# CHECK: c.ngt.d $f12,$f14
-0x3f 0x60 0x2e 0x46
+0x3f 0x30 0x27 0x46
# CHECK: c.ngt.s $f6,$f7
0x3f 0x30 0x07 0x46
# CHECK: c.ole.d $f12,$f14
-0x36 0x60 0x2e 0x46
+0x36 0x30 0x27 0x46
# CHECK: c.ole.s $f6,$f7
0x36 0x30 0x07 0x46
# CHECK: c.olt.d $f12,$f14
-0x34 0x60 0x2e 0x46
+0x34 0x30 0x27 0x46
# CHECK: c.olt.s $f6,$f7
0x34 0x30 0x07 0x46
# CHECK: c.seq.d $f12,$f14
-0x3a 0x60 0x2e 0x46
+0x3a 0x30 0x27 0x46
# CHECK: c.seq.s $f6,$f7
0x3a 0x30 0x07 0x46
# CHECK: c.sf.d $f12,$f14
-0x38 0x60 0x2e 0x46
+0x38 0x30 0x27 0x46
# CHECK: c.sf.s $f6,$f7
0x38 0x30 0x07 0x46
# CHECK: c.ueq.d $f12,$f14
-0x33 0x60 0x2e 0x46
+0x33 0x30 0x27 0x46
# CHECK: c.ueq.s $f28,$f18
0x33 0xe0 0x12 0x46
# CHECK: c.ule.d $f12,$f14
-0x37 0x60 0x2e 0x46
+0x37 0x30 0x27 0x46
# CHECK: c.ule.s $f6,$f7
0x37 0x30 0x07 0x46
# CHECK: c.ult.d $f12,$f14
-0x35 0x60 0x2e 0x46
+0x35 0x30 0x27 0x46
# CHECK: c.ult.s $f6,$f7
0x35 0x30 0x07 0x46
# CHECK: c.un.d $f12,$f14
-0x31 0x60 0x2e 0x46
+0x31 0x30 0x27 0x46
# CHECK: c.un.s $f6,$f7
0x31 0x30 0x07 0x46
# CHECK: ceil.w.d $f12,$f14
-0x0e 0x73 0x20 0x46
+0x8e 0x38 0x20 0x46
# CHECK: ceil.w.s $f6,$f7
-0x0e 0x73 0x20 0x46
+0x8e 0x38 0x00 0x46
# CHECK: cfc1 a2,$7
0x00 0x38 0x46 0x44
@@ -178,28 +178,28 @@
0xa1 0x39 0x00 0x46
# CHECK: cvt.d.w $f12,$f14
-0x21 0x73 0x80 0x46
+0xa1 0x39 0x80 0x46
# CHECK: cvt.l.d $f12,$f14
-0x05 0x73 0x20 0x46
+0xa5 0x39 0x20 0x46
# CHECK: cvt.l.s $f6,$f7
0xa5 0x39 0x00 0x46
# CHECK: cvt.s.d $f12,$f14
-0x20 0x73 0x20 0x46
+0xa0 0x39 0x20 0x46
# CHECK: cvt.s.w $f6,$f7
0xa0 0x39 0x80 0x46
# CHECK: cvt.w.d $f12,$f14
-0x24 0x73 0x20 0x46
+0xa4 0x39 0x20 0x46
# CHECK: cvt.w.s $f6,$f7
0xa4 0x39 0x00 0x46
# CHECK: floor.w.d $f12,$f14
-0x0f 0x73 0x20 0x46
+0x8f 0x39 0x20 0x46
# CHECK: floor.w.s $f6,$f7
0x8f 0x39 0x00 0x46
@@ -213,7 +213,7 @@
# CHECK: jal 00000530
0x4c 0x01 0x00 0x0c
-# CHECK: jalr a3
+# CHECK: jalr a2,a3
0x09 0xf8 0xe0 0x00
# CHECK: jr a3
@@ -267,8 +267,8 @@
# CHECK: mflo a1
0x12 0x28 0x00 0x00
-# CHECK: mov.d $f6,$f8
-0x86 0x41 0x20 0x46
+# CHECK: mov.d $f12,$f14
+0x86 0x39 0x20 0x46
# CHECK: mov.s $f6,$f7
0x86 0x39 0x00 0x46
@@ -291,11 +291,11 @@
# CHECK: mtlo a3
0x13 0x00 0xe0 0x00
-# CHECK: mul.d $f8,$f12,$f14
-0x02 0x62 0x2e 0x46
+# CHECK: mul.d $f9,$f12,$f14
+0x42 0x32 0x27 0x46
# CHECK: mul.s $f9,$f6,$f7
-0x02 0x62 0x07 0x46
+0x42 0x32 0x07 0x46
# CHECK: mul t1,a2,a3
0x02 0x48 0xc7 0x70
@@ -307,7 +307,7 @@
0x19 0x00 0x65 0x00
# CHECK: neg.d $f12,$f14
-0x07 0x73 0x20 0x46
+0x87 0x39 0x20 0x46
# CHECK: neg.s $f6,$f7
0x87 0x39 0x00 0x46
@@ -340,7 +340,7 @@
0x46 0x48 0xe6 0x00
# CHECK: round.w.d $f12,$f14
-0x0c 0x73 0x20 0x46
+0x8c 0x39 0x20 0x46
# CHECK: round.w.s $f6,$f7
0x8c 0x39 0x00 0x46
@@ -385,7 +385,7 @@
0x2b 0x18 0x65 0x00
# CHECK: sqrt.d $f12,$f14
-0x04 0x73 0x20 0x46
+0x84 0x39 0x20 0x46
# CHECK: sqrt.s $f6,$f7
0x84 0x39 0x00 0x46
@@ -405,8 +405,8 @@
# CHECK: srlv v0,v1,a1
0x06 0x10 0xa3 0x00
-# CHECK: sub.d $f8,$f12,$f14
-0x01 0x62 0x2e 0x46
+# CHECK: sub.d $f9,$f12,$f14
+0x41 0x32 0x27 0x46
# CHECK: sub.s $f9,$f6,$f7
0x41 0x32 0x07 0x46
@@ -427,7 +427,7 @@
0xcf 0x01 0x00 0x00
# CHECK: trunc.w.d $f12,$f14
-0x0d 0x73 0x20 0x46
+0x8d 0x39 0x20 0x46
# CHECK: trunc.w.s $f6,$f7
0x8d 0x39 0x00 0x46
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