[llvm-commits] [llvm] r158743 - in /llvm/trunk: lib/CodeGen/PeepholeOptimizer.cpp lib/Target/PowerPC/PPCInstrInfo.cpp lib/Target/PowerPC/PPCInstrInfo.h test/CodeGen/PowerPC/coalesce-ext.ll
Hal Finkel
hfinkel at anl.gov
Tue Jun 19 14:39:38 PDT 2012
On Tue, 19 Jun 2012 21:14:34 -0000
Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> Author: stoklund
> Date: Tue Jun 19 16:14:34 2012
> New Revision: 158743
>
> URL: http://llvm.org/viewvc/llvm-project?rev=158743&view=rev
> Log:
> Implement PPCInstrInfo::isCoalescableExtInstr().
Thanks!
-Hal
>
> The PPC::EXTSW instruction preserves the low 32 bits of its input,
> just like some of the x86 instructions. Use it to reduce register
> pressure when the low 32 bits have multiple uses.
>
> This requires a small change to PeepholeOptimizer since EXTSW takes a
> 64-bit input register.
>
> This is related to PR5997.
>
> Added:
> llvm/trunk/test/CodeGen/PowerPC/coalesce-ext.ll
> Modified:
> llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
>
> Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=158743&r1=158742&r2=158743&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++
> llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Jun 19 16:14:34 2012
> @@ -156,6 +156,14 @@ if (!DstRC)
> return false;
>
> + // The ext instr may be operating on a sub-register of SrcReg as
> well.
> + // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a
> 64-bit
> + // register.
> + // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only
> uses of
> + // SrcReg:SubIdx should be replaced.
> + bool UseSrcSubIdx = TM->getRegisterInfo()->
> + getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
> +
> // The source has other uses. See if we can replace the other uses
> with use of // the result of the extension.
> SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
> @@ -184,6 +192,10 @@
> continue;
> }
>
> + // Only accept uses of SrcReg:SubIdx.
> + if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
> + continue;
> +
> // It's an error to translate this:
> //
> // %reg1025 = <sext> %reg1024
> @@ -259,10 +271,14 @@
> }
>
> unsigned NewVR = MRI->createVirtualRegister(RC);
> - BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
> - TII->get(TargetOpcode::COPY), NewVR)
> + MachineInstr *Copy = BuildMI(*UseMBB, UseMI,
> UseMI->getDebugLoc(),
> + TII->get(TargetOpcode::COPY),
> NewVR) .addReg(DstReg, 0, SubIdx);
> -
> + // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx
> is set.
> + if (UseSrcSubIdx) {
> + Copy->getOperand(0).setSubReg(SubIdx);
> + Copy->getOperand(0).setIsUndef();
> + }
> UseMO->setReg(NewVR);
> ++NumReuse;
> Changed = true;
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=158743&r1=158742&r2=158743&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jun 19 16:14:34
> 2012 @@ -79,6 +79,22 @@
> return new PPCScoreboardHazardRecognizer(II, DAG);
> }
> +
> +// Detect 32 -> 64-bit extensions where we may reuse the low
> sub-register. +bool PPCInstrInfo::isCoalescableExtInstr(const
> MachineInstr &MI,
> + unsigned &SrcReg, unsigned
> &DstReg,
> + unsigned &SubIdx) const {
> + switch (MI.getOpcode()) {
> + default: return false;
> + case PPC::EXTSW:
> + case PPC::EXTSW_32_64:
> + SrcReg = MI.getOperand(1).getReg();
> + DstReg = MI.getOperand(0).getReg();
> + SubIdx = PPC::sub_32;
> + return true;
> + }
> +}
> +
> unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const {
> switch (MI->getOpcode()) {
>
> Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=158743&r1=158742&r2=158743&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original) +++
> llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Tue Jun 19 16:14:34 2012
> @@ -92,6 +92,9 @@ CreateTargetPostRAHazardRecognizer(const
> InstrItineraryData *II, const ScheduleDAG *DAG) const;
>
> + bool isCoalescableExtInstr(const MachineInstr &MI,
> + unsigned &SrcReg, unsigned &DstReg,
> + unsigned &SubIdx) const;
> unsigned isLoadFromStackSlot(const MachineInstr *MI,
> int &FrameIndex) const;
> unsigned isStoreToStackSlot(const MachineInstr *MI,
>
> Added: llvm/trunk/test/CodeGen/PowerPC/coalesce-ext.ll
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/coalesce-ext.ll?rev=158743&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PowerPC/coalesce-ext.ll (added) +++
> llvm/trunk/test/CodeGen/PowerPC/coalesce-ext.ll Tue Jun 19 16:14:34
> 2012 @@ -0,0 +1,17 @@ +; RUN: llc -march=ppc64 < %s | FileCheck %s
> +; Check that the peephole optimizer knows about sext and zext
> instructions. +; CHECK: test1sext
> +define i32 @test1sext(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
> + %C = add i64 %A, %B
> + ; CHECK: add [[SUM:r[0-9]+]], r3, r4
> + %D = trunc i64 %C to i32
> + %E = shl i64 %C, 32
> + %F = ashr i64 %E, 32
> + ; CHECK: extsw [[EXT:r[0-9]+]], [[SUM]]
> + store volatile i64 %F, i64 *%P2
> + ; CHECK: std [[EXT]]
> + store volatile i32 %D, i32* %P
> + ; Reuse low bits of extended register, don't extend live range of
> SUM.
> + ; CHECK: stw [[EXT]]
> + ret i32 %D
> +}
>
>
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--
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory
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