[llvm-commits] [llvm] r158551 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/iabs.ll test/CodeGen/ARM/thumb2-it-block.ll
Manman Ren
mren at apple.com
Fri Jun 15 14:32:12 PDT 2012
Author: mren
Date: Fri Jun 15 16:32:12 2012
New Revision: 158551
URL: http://llvm.org/viewvc/llvm-project?rev=158551&view=rev
Log:
ARM: optimization for sub+abs.
This patch will optimize abs(x-y)
FROM
sub, movs, rsbmi
TO
subs, rsbmi
For abs, we will use cmp instead of movs. This is necessary because we already
have an existing peephole pass which optimizes away cmp following sub.
rdar: 11633193
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/test/CodeGen/ARM/iabs.ll
llvm/trunk/test/CodeGen/ARM/thumb2-it-block.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=158551&r1=158550&r2=158551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 15 16:32:12 2012
@@ -6808,9 +6808,6 @@
MachineRegisterInfo &MRI = Fn->getRegInfo();
// In Thumb mode S must not be specified if source register is the SP or
// PC and if destination register is the SP, so restrict register class
- unsigned NewMovDstReg = MRI.createVirtualRegister(isThumb2 ?
- (const TargetRegisterClass*)&ARM::rGPRRegClass :
- (const TargetRegisterClass*)&ARM::GPRRegClass);
unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
(const TargetRegisterClass*)&ARM::rGPRRegClass :
(const TargetRegisterClass*)&ARM::GPRRegClass);
@@ -6827,12 +6824,10 @@
// fall through to SinkMBB
RSBBB->addSuccessor(SinkBB);
- // insert a movs at the end of BB
- BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2MOVr : ARM::MOVr),
- NewMovDstReg)
- .addReg(ABSSrcReg, RegState::Kill)
- .addImm((unsigned)ARMCC::AL).addReg(0)
- .addReg(ARM::CPSR, RegState::Define);
+ // insert a cmp at the end of BB
+ AddDefaultPred(BuildMI(BB, dl,
+ TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
+ .addReg(ABSSrcReg).addImm(0));
// insert a bcc with opposite CC to ARMCC::MI at the end of BB
BuildMI(BB, dl,
@@ -6844,7 +6839,7 @@
// by if-conversion pass
BuildMI(*RSBBB, RSBBB->begin(), dl,
TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
- .addReg(NewMovDstReg, RegState::Kill)
+ .addReg(ABSSrcReg, RegState::Kill)
.addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
// insert PHI in SinkBB,
@@ -6852,7 +6847,7 @@
BuildMI(*SinkBB, SinkBB->begin(), dl,
TII->get(ARM::PHI), ABSDstReg)
.addReg(NewRsbDstReg).addMBB(RSBBB)
- .addReg(NewMovDstReg).addMBB(BB);
+ .addReg(ABSSrcReg).addMBB(BB);
// remove ABS instruction
MI->eraseFromParent();
Modified: llvm/trunk/test/CodeGen/ARM/iabs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/iabs.ll?rev=158551&r1=158550&r2=158551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/iabs.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/iabs.ll Fri Jun 15 16:32:12 2012
@@ -10,7 +10,25 @@
%b = icmp sgt i32 %a, -1
%abs = select i1 %b, i32 %a, i32 %tmp1neg
ret i32 %abs
-; CHECK: movs r0, r0
+; CHECK: cmp
; CHECK: rsbmi r0, r0, #0
; CHECK: bx lr
}
+
+; rdar://11633193
+;; 3 instructions will be generated for abs(a-b):
+;; subs
+;; rsbmi
+;; bx
+define i32 @test2(i32 %a, i32 %b) nounwind readnone ssp {
+entry:
+; CHECK: test2
+; CHECK: subs
+; CHECK-NEXT: rsbmi
+; CHECK-NEXT: bx
+ %sub = sub nsw i32 %a, %b
+ %cmp = icmp sgt i32 %sub, -1
+ %sub1 = sub nsw i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
Modified: llvm/trunk/test/CodeGen/ARM/thumb2-it-block.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb2-it-block.ll?rev=158551&r1=158550&r2=158551&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/thumb2-it-block.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/thumb2-it-block.ll Fri Jun 15 16:32:12 2012
@@ -3,10 +3,10 @@
define i32 @test(i32 %a, i32 %b) {
entry:
-; CHECK: movs.w
+; CHECK: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsbmi
-; CHECK-NEXT: movs.w
+; CHECK-NEXT: cmp
; CHECK-NEXT: it mi
; CHECK-NEXT: rsbmi
%cmp1 = icmp slt i32 %a, 0
More information about the llvm-commits
mailing list