[llvm-commits] [llvm] r158432 - /llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

[Akira Hatanaka]

Author: ahatanak
Date: Wed Jun 13 20:17:59 2012
New Revision: 158432

URL: http://llvm.org/viewvc/llvm-project?rev=158432&view=rev
Log:
Add AT to the list of registers clobbered by branches so that it is available
as a scratch register when they are expanded to long branches.

Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=158432&r1=158431&r2=158432&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Jun 13 20:17:59 2012
@@ -561,6 +561,7 @@
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
+  let Defs = [AT];
 }
 
 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
@@ -572,6 +573,7 @@
   let isBranch = 1;
   let isTerminator = 1;
   let hasDelaySlot = 1;
+  let Defs = [AT];
 }
 
 // SetCC
@@ -601,6 +603,7 @@
   let hasDelaySlot = 1;
   let Predicates = [RelocStatic, HasStandardEncoding];
   let DecoderMethod = "DecodeJumpTarget";
+  let Defs = [AT];
 }
 
 // Unconditional branch
@@ -614,6 +617,7 @@
   let isBarrier = 1;
   let hasDelaySlot = 1;
   let Predicates = [RelocPIC, HasStandardEncoding];
+  let Defs = [AT];
 }
 
 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,